EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 382

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

11–50
Table 11–16. Dedicated JTAG Pins
Stratix III Device Handbook, Volume 1
TDI
TDO
TMS
TCK
TRST
Pin Name
N/A
N/A
N/A
N/A
N/A
User Mode
Table 11–16
and during configuration to prevent accidental loading of JTAG instructions. The TDI,
TMS, and TRST have weak internal pull-up resistors while TCK has a weak internal
pull-down resistor (typically 25 kΩ). If you plan to use the SignalTap
array analyzer, you must connect the JTAG pins of the Stratix III device to a JTAG
header on your board.
Input
Output
Input
Input
Input
Pin Type
describes the dedicated JTAG pins. JTAG pins must be kept stable before
Serial input pin for instructions as well as test and programming data. Data is
shifted in on the rising edge of TCK. The TDI pin is powered by the
2.5-V/3.0-V/3.3-V V
If the JTAG interface is not required on the board, you can disable the JTAG circuitry
by connecting this pin to V
Serial data output pin for instructions as well as test and programming data. Data is
shifted out on the falling edge of TCK. The pin is tri-stated if data is not being
shifted out of the device. The TDO pin is powered by V
connecting a JTAG chain with multiple voltages across the devices in the chain,
refer to the chapter IEEE 1149.1 (JTAG) Boundary Scan Testing in Stratix III Devices
chapter in volume 1 of the Stratix III Device Handbook.
If the JTAG interface is not required on the board, you can disable the JTAG circuitry
by leaving this pin unconnected.
Input pin that provides the control signal to determine the transitions of the TAP
controller state machine. Transitions within the state machine occur on the rising
edge of TCK. Therefore, TMS must be set up before the rising edge of TCK. TMS is
evaluated on the rising edge of TCK. The TMS pin is powered by the
2.5-V/3.0-V/3.3-V V
If the JTAG interface is not required on the board, you can disable the JTAG circuitry
by connecting this pin to V
The clock input to the BST circuitry. Some operations occur at the rising edge, while
others occur at the falling edge. The TCK pin is powered by the 2.5-V/3.0-V/3.3-V
V
It is expected that the clock input waveform have a nominal 50% duty cycle.
If the JTAG interface is not required on the board, you can disable the JTAG circuitry
by connecting TCK to GND.
Active-low input to asynchronously reset the boundary-scan circuit. The TRST pin
is optional according to IEEE Std. 1149.1. The TRST pin is powered by the
2.5-V/3.0-V/3.3-V V
You should hold TMS at 1 or you should keep TCK static while TRST is changed
from 0 to 1.
If the JTAG interface is not required on the board, you can disable the JTAG circuitry
by connecting the TRST pin to GND.
C CPD
supply.
C CP D
CCPD
C CP D
supply.
.
supply.
CCPD
C CP D
.
.
Description
Chapter 11: Configuring Stratix III Devices
CCP D
© March 2011 Altera Corporation
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embedded logic