EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 210

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

7–6
Figure 7–1. I/O Banks for Stratix III Devices
Notes to
(1) Differential HSTL and SSTL outputs are not true differential outputs. They use two single-ended outputs with the second output programmed as
(2) Column and row I/O differential HSTL and SSTL inputs use LVDS differential input buffers without OCT R
(3) Column and row I/O supports emulated LVDS output buffer.
(4) Column I/O supports PCI/PCI-X with on-chip clamp diode, and row I/O supports PCI/PCI-X with external clamp diode.
(5) Clock inputs on column I/O are powered by V
(6) Row I/O supports the true LVDS output buffer.
(7) Column and row I/O banks support LVPECL standards for input operation on dedicated clock input pins.
(8)
(9) 3.0-V PCI/PCI-X and 3.3-V LVTTL/LVCMOS outputs are not supported in the same I/O bank.
Stratix III Device Handbook, Volume 1
inverted.
single-ended clock input. All outputs use the corresponding bank V
Figure 7–1
Figure
Bank 3A
Bank 8A
is a top view of the silicon die that corresponds to a reverse view for flip chip packages. It is a graphical representation only.
7–1:
I/O banks 3A, 3B, and 3C support all
single-ended and differential input
and output operation except LVPECL,,
which is supported on clk input pins only.
I/O banks 8A, 8B, and 8C support all
single-ended and differential input
and output operation except LVPECL,
which is supported on clk input pins only.
Bank 3B
Bank 8B
Row I/O banks support LVTTL, LVCMOS, 2.5-V, 1.8-V,
1.5-V, 1.2-V, SSTL-2 Class I & II, SSTL-18 Class I & II,
SSTL-15 Class I, HSTL-18 Class I & II, HSTL-15 Class I,
HSTL-12 Class I, LVDS, RSDS, mini-LVDS, differential
SSTL-2 Class I & II, differential SSTL-18 Class I & II,
differential SSTL-15 Class I, differential HSTL-18 Class I &
II, differential HSTL-15 Class I and differential HSTL-12
Class I standards for input and output operation.
LVPECL standards for input operation on dedicated clock input pins.
CCCLKIN
(Note
Bank 3C
when configured as differential clock input. They are powered by V
Bank 8C
1), (2), (3), (4), (5), (6), (7), (8),
CCIO
.
Bank 7C
Bank 4C
I/O banks 7A, 7B, and 7C support all
single-ended and differential input
and output operation except LVPECL,
which is supported on clk input pins only.
I/O banks 4A, 4B, and 4C support all
single-ended and differential input
and output operation except LVPECL,
which is supported on clk input pins only.
Bank 4B
(9)
Bank 7B
Chapter 7: Stratix III Device I/O Features
D
support.
© July 2010 Altera Corporation
Bank 4A
Bank 7A
CCIO
when configured as
Stratix III I/O Banks