EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 268

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

8–20
Figure 8–10. DQS and CQn Pins and DQS Phase-Shift Circuitry
Notes to
(1) For possible reference input clock pins for each DLL, refer
(2) You can configure each DQS/CQn signal pair with a phase shift based on one of two possible DLL output settings.
Stratix III Device Handbook, Volume 1
DQS/CQ
DQS/CQ
Pin
CQn
Pin
CQn
Pin
Pin
Figure
8–10:
t
t
t
t
Phase-Shift
Phase-Shift
DQS phase-shift circuitry is connected to the DQS logic blocks that control each
DQS/CQ or CQn pin. The DQS logic blocks allow the DQS delay settings to be
updated concurrently at every DQS/CQ or CQn pin.
Reference
Reference
Clock (2)
Circuitry
Circuitry
Clock (2)
DQS
IOE
IOE
DQS
IOE
IOE
DLL
DLL
to
to
to
to
to IOE
CQn
Pin
t
DQS/CQ
to IOE
Pin
t
DQS/CQ
to IOE
Pin
t
to IOE
CQn
Pin
t
to“DLL” on page
DQS Logic
Blocks
to IOE
CQn
(Note 1)
Pin
t
8–21.
DQS/CQ
to IOE
Pin
Chapter 8: External Memory Interfaces in Stratix III Devices
t
DQS/CQ
to IOE
Pin
t
to IOE
CQn
Pin
t
Stratix III External Memory Interface Features
Phase-Shift
Phase-Shift
Reference
Reference
Clock (2)
Clock (2)
Circuitry
Circuitry
DQS
DQS
DLL
DLL
IOE
IOE
IOE
IOE
to
to
to
to
© March 2010 Altera Corporation
DQS Logic
Blocks
t
t
t
t
DQS/CQ
DQS/CQ
CQn
CQn
Pin
Pin
Pin
Pin