EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 118

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

5–12
Multiplier and First-Stage Adder
Stratix III Device Handbook, Volume 1
Shift registers are useful in DSP functions such as FIR filters. When implementing
18 × 18 or smaller width multipliers, you do not need external logic to create the shift
register chain because the input shift registers are internal to the DSP block. This
implementation significantly reduces the logical element (LE) resources required,
avoids routing congestion, and results in predictable timing.
The first multiplier in every half DSP block (top- and bottom-half) in Stratix III
devices has a multiplexer for the first multiplier B-input (lower-leg input) register to
select between general routing and loopback, as shown in
mode, the most significant 18-bit registered outputs are connected as feedback to the
multiplier input of the first top multiplier in each half DSP block. Loopback modes are
used by recursive filters where the previous output is needed to compute the current
output.
The loopback mode is described in detail in
page
Table 5–3
Table 5–3. Input Register Modes
The multiplier stage natively supports 9 × 9, 12 × 12, 18 × 18, or 36 × 36 multipliers.
Other wordlengths are padded up to the nearest appropriate native wordlength; for
example, 16 × 16 would be padded up to use 18 × 18. Refer to
Multiplier Modes” on page 5–15
multiplier, a single DSP block can perform many multiplications in parallel.
Each multiplier operand can be a unique signed or unsigned number. Two dynamic
signals, signa and signb, control the representation of each operand, respectively. A
logic 1 value on the signa/signb signal indicates that data A/data B is a
signed number; a logic 0 value indicates an unsigned number.
sign of the multiplication result for the various operand sign representations. The
result of the multiplication is signed if any one of the operands is a signed value.
Table 5–4. Multiplier Sign Representation
Parallel input
Shift register input
Loopback input
Notes to
(1) The multiplier operand input wordlengths are statically configured at compile time.
(2) Available only on the A-operand.
(3) Only one loopback input is allowed per Half-Block. See
Register Input Mode
Unsigned (logic 0)
Unsigned (logic 0)
5–21.
Signed (logic 1)
Signed (logic 1)
Table
(signa Value)
lists the input register modes for the DSP block.
Data A
5–3:
(3)
(2)
(1)
9 × 9
v
—
—
for more details. Depending on the data width of the
Unsigned (logic 0)
Unsigned (logic 0)
Signed (logic 1)
Signed (logic 1)
(signb Value)
Data B
12 × 12
v
—
—
Figure 5–15
“Two-Multiplier Adder Sum Mode” on
18 × 18
for details.
Chapter 5: DSP Blocks in Stratix III Devices
v
v
v
Figure
© March 2010 Altera Corporation
DSP Block Resource Descriptions
“Independent
36 × 36
5–6. In loopback
Table 5–4
v
—
—
Unsigned
Signed
Signed
Signed
Result
lists the
Double
v
—
—