EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 362

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

11–30
Figure 11–14. Multi-Device PS Configuration Using an External Host
Note to
(1) Connect the resistor to a supply that provides an acceptable input signal for all Stratix III devices on the chain. V
Stratix III Device Handbook, Volume 1
meet the V
Figure
(MAX II Device or
Microprocessor)
External Host
ADDR
IH
11–14:
Memory
specification of the I/O on the external host. It is recommended to power up all configuration systems’ I/O with V
DATA0
When the device is in user mode, you can initiate a reconfiguration by transitioning
the nCONFIG pin low-to-high. The nCONFIG pin must be low for at least 2 μs. When
nCONFIG is pulled low, the device also pulls nSTATUS and CONF_DONE low and all
I/O pins are tri-stated. When nCONFIG returns to a logic high level and nSTATUS is
released by the device, reconfiguration begins.
Figure 11–14
circuit is similar to the PS configuration circuit for a single device, except Stratix III
devices are cascaded for multi-device configuration.
In multi-device PS configuration, the first device’s nCE pin is connected to GND while
its nCEO pin is connected to nCE of the next device in the chain. The last device’s nCE
input comes from the previous device, while its nCEO pin is left floating. After the first
device completes configuration in a multi-device configuration chain, its nCEO pin
drives low to activate the second device’s nCE pin, which prompts the second device
to begin configuration. The second device in the chain begins configuration within
one clock cycle. Therefore, the transfer of data destinations is transparent to the
MAX II device. All other configuration pins (nCONFIG, nSTATUS, DCLK, DATA0, and
CONF_DONE) are connected to every device in the chain. Configuration signals can
require buffering to ensure signal integrity and prevent clock skew problems. Ensure
that the DCLK and DATA lines are buffered for every fourth device. Because all device
CONF_DONE pins are tied together, all devices initialize and enter user mode at the
same time.
Since all nSTATUS and CONF_DONE pins are tied together, if any device detects an
error, configuration stops for the entire chain and you must reconfigure the entire
chain. For example, if the first device flags an error on nSTATUS, it resets the chain by
pulling its nSTATUS pin low. This behavior is similar to a single device detecting an
error.
V CCPGM (1)
10 k
Ω
V CCPGM (1)
shows how to configure multiple devices using a MAX II device. This
10 k
GND
Ω
CONF_DONE
nSTATUS
nCE
DATA0
nCONFIG
DCLK
Stratix III Device 1
MSEL2
MSEL1
MSEL0
nCEO
GND
V
CCPGM
Chapter 11: Configuring Stratix III Devices
CONF_DONE
nSTATUS
nCE
DATA0
nCONFIG
DCLK
Stratix III Device 2
© March 2011 Altera Corporation
CCPGM
MSEL2
MSEL1
MSEL0
Passive Serial Configuration
nCEO
must be high enough to
N.C.
CCPGM
GND
V
CCPGM
.