EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 290
EP3SL150F1152C3N
Manufacturer Part Number
EP3SL150F1152C3N
Description
IC STRATX III FPGA 150K 1152FBGA
Manufacturer
Altera
Series
Stratix® IIIr
Datasheets
1.EP3SL150F780C4N.pdf
(16 pages)
2.EP3SL150F780C4N.pdf
(332 pages)
3.EP3SL150F780C4N.pdf
(456 pages)
Specifications of EP3SL150F1152C3N
Number Of Logic Elements/cells
142500
Number Of Labs/clbs
5700
Total Ram Bits
6390
Number Of I /o
744
Voltage - Supply
0.86 V ~ 1.15 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
For Use With
544-2568 - KIT DEVELOPMENT STRATIX III
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-2408
EP3SL150F1152C3NES
EP3SL150F1152C3NES
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3SL150F1152C3N
Manufacturer:
ALTERA
Quantity:
490
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8–42
Table 8–12. DQS Configuration Block Bit Sequence
IOE Features
Stratix III Device Handbook, Volume 1
11..14
15..18
19..22
27..29
30..33
34..36
7..10
0..3
4..6
Bit
23
24
25
26
37
38
39
40
41
42
43
44
45
46
47
f
Table 8–12
This section briefly describes how OCT, programmable delay chains, programmable
output delay, slew rate adjustment, and programmable drive strength are useful in
memory interfaces.
For more information about the features listed below, refer to the
Features
chapter.
lists the DQS configuration block bit sequence.
dqsenablectrlphasesetting[0..3]
enadqsenablephasetransferreg
resyncinputphasesetting[0..3]
dqsoutputphasesetting[0..3]
dqsbusoutdelaysetting[0..3]
dqsenabledelaysetting[0..2]
dqsinputphasesetting[0..2]
dqoutputphasesetting[0..3]
enaoutputcycledelaysetting
enaoutputphasetransferreg
dqsbusoutfinedelaysetting
enainputcycledelaysetting
dqsenablefinedelaysetting
enainputphasetransferreg
dqsenablectrlphaseinvert
enaoctcycledelaysetting
enaoctphasetransferreg
resyncinputphaseinvert
octdelaysetting1[0..3]
octdelaysetting2[0..2]
dqsoutputphaseinvert
dqoutputphaseinvert
dividerphasesetting
enadataoutbypass
Chapter 8: External Memory Interfaces in Stratix III Devices
Bit Name
Stratix III External Memory Interface Features
© March 2010 Altera Corporation
Stratix III Device I/O
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