EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 226
![IC STRATX III FPGA 150K 1152FBGA](/photos/6/72/67293/544-1152-fbga_sml.jpg)
EP3SL150F1152C3N
Manufacturer Part Number
EP3SL150F1152C3N
Description
IC STRATX III FPGA 150K 1152FBGA
Manufacturer
Altera
Series
Stratix® IIIr
Datasheets
1.EP3SL150F780C4N.pdf
(16 pages)
2.EP3SL150F780C4N.pdf
(332 pages)
3.EP3SL150F780C4N.pdf
(456 pages)
Specifications of EP3SL150F1152C3N
Number Of Logic Elements/cells
142500
Number Of Labs/clbs
5700
Total Ram Bits
6390
Number Of I /o
744
Voltage - Supply
0.86 V ~ 1.15 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
For Use With
544-2568 - KIT DEVELOPMENT STRATIX III
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-2408
EP3SL150F1152C3NES
EP3SL150F1152C3NES
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3SL150F1152C3N
Manufacturer:
ALTERA
Quantity:
490
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7–22
Stratix III Device Handbook, Volume 1
Table 7–8. Selectable I/O Standards with On-Chip Series Termination With or Without Calibration
Expanded On-Chip Series Termination with Calibration
OCT calibration circuits always adjust OCT R
connected to the RUP and RDN pins, it is possible to achieve different OCT R
besides the 25- and 50- Ω resistors. Theoretically you can always change the resistance
connected to the RUP and RDN pins accordingly if you require a different OCT R
value. Practically, the OCT R
due to the output buffer size and granularity limitations.
OCT R
allows discrete OCT R
the closest discrete value of OCT R
to your system to get the closest timing and IBIS model information. For example, if
you use 20- Ω OCT R
calibration setting in the Quartus II software to get the closest timing and IBIS model
information.
3.3-V LVTTL/LVCMOS
3.0-V LVTTL/LVCMOS
2.5-V LVTTL/LVCMOS
1.8-V LVTTL/LVCMOS
1.5-V LVTTL/LVCMOS
1.2-V LVTTL/LVCMOS
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
SSTL-15 Class I
SSTL-15 Class II
HSTL-18 Class I
HSTL-18 Class II
HSTL-15 Class I
HSTL-15 Class II
HSTL-12 Class I
HSTL-12 Class II
S
with calibration supported in Stratix III devices.The Quartus II software only
I/O Standard
S
with calibration in your system, you can select 25- Ω OCT R
S
calibration settings of 25 Ω , 40 Ω , 50 Ω , and 60 Ω . You can select
S
range, which Stratix III devices can support, is limited
S
with calibration settings in the Quartus II software
Row I/O
50
25
50
25
50
25
50
25
50
50
50
25
50
25
50
—
50
25
50
—
50
—
On-Chip Series Termination Setting
S
to match the external resistors
Chapter 7: Stratix III Device I/O Features
Table 7–9
Column I/O
© July 2010 Altera Corporation
50
25
50
25
50
25
50
25
50
25
50
25
50
25
50
25
50
25
50
25
50
25
50
25
shows expanded
S
OCT Support
values
Unit
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
S
S
with
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