EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 132
![IC STRATX III FPGA 150K 1152FBGA](/photos/6/72/67293/544-1152-fbga_sml.jpg)
EP3SL150F1152C3N
Manufacturer Part Number
EP3SL150F1152C3N
Description
IC STRATX III FPGA 150K 1152FBGA
Manufacturer
Altera
Series
Stratix® IIIr
Datasheets
1.EP3SL150F780C4N.pdf
(16 pages)
2.EP3SL150F780C4N.pdf
(332 pages)
3.EP3SL150F780C4N.pdf
(456 pages)
Specifications of EP3SL150F1152C3N
Number Of Logic Elements/cells
142500
Number Of Labs/clbs
5700
Total Ram Bits
6390
Number Of I /o
744
Voltage - Supply
0.86 V ~ 1.15 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
For Use With
544-2568 - KIT DEVELOPMENT STRATIX III
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-2408
EP3SL150F1152C3NES
EP3SL150F1152C3NES
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3SL150F1152C3N
Manufacturer:
ALTERA
Quantity:
490
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5–26
High Precision Multiplier Adder
Stratix III Device Handbook, Volume 1
In the high precision multiplier adder configuration shown in
block can implement two two-multiplier adders, with multiplier precision of 18 × 36
(one two-multiplier adder per DSP half block). This mode is useful in filtering or FFT
applications where a data path greater than 18 bits is required, yet 18 bits is sufficient
for the coefficient precision. This can occur in cases where that data has a high
dynamic range. If the coefficients are fixed, as in FFT and most filter applications, the
precision of 18 bits will provide a dynamic range over 100 dB if the largest coefficient
is normalized to the maximum 18-bit representation.
In these situations, the data path can be up to 36 bits, allowing ample headroom to bit
growth, or gain changes in the signal source without loss of precision. This mode is
also extremely useful in single precision block floating point applications.
The high precision multiplier adder is preformed in two stages. The 18 × 36 multiply
is decomposed into two 18 × 18 multipliers. The multiplier with the LSB of the data
source is performed unsigned, while the multiplier with the MSB of the data source
can be signed or signed. The latter multiplier has its result left shifted by 18 bits prior
to the first adder stage, creating an effective 18 × 36 multiplier. The results of these
two adder blocks are then summed in the second stage adder block to produce the
final result.
Equation 5–5. High Precision Multiplier Adder Equation
P
0
= A[17..0] ´ B[35..0] and P
Z[54..0] = P
0
[53..0] + P
1
1
= C[17..0] ´ D[35..0]
[53..0] where
Chapter 5: DSP Blocks in Stratix III Devices
© March 2010 Altera Corporation
Figure
Operational Mode Descriptions
5–18, the DSP
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