EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 97

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

Chapter 4: TriMatrix Embedded Memory Blocks in Stratix III Devices
Overview
Figure 4–16. Stratix III True Dual-Port Timing Waveform
Shift-Register Mode
© May 2009 Altera Corporation
q_a (asynch)
q_b (asynch)
address_a
address_b
wren_a
wren_b
data_a
clk_a
clk_b
din-1
an-1
doutn-1
All Stratix III memory blocks support shift register mode. Embedded memory block
configurations can implement shift registers for digital signal processing (DSP)
applications, such as finite impulse response (FIR) filters, pseudo-random number
generators, multi-channel filtering, and auto- and cross-correlation functions. These
and other DSP applications require local data storage, traditionally implemented with
standard flipflops that quickly exhaust many logic cells for large shift registers. A
more efficient alternative is to use embedded memory as a shift-register block, which
saves logic cell and routing resources.
The size of a shift register (w × m × n) is determined by the input data width (w), the
length of the taps (m), and the number of taps (n). You can cascade memory blocks to
implement larger shift registers.
bn
din-1
din
an
doutn
din
b0
a0
dout0
a1
dout0
dout1
b1
a2
dout2
a3
dout3
dout1
b2
din4
a4
Stratix III Device Handbook, Volume 1
din4
din5
a5
dout2
din5
b3
din6
a6
4–17