EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 310

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

9–16
Figure 9–16. Bit-Order and Word Boundary for One Differential Channel
Note to
(1) These are only functional waveforms and are not intended to convey timing information.
Stratix III Device Handbook, Volume 1
Transmitter Channel
Operation (x8 Mode)
Operation (x4 Mode)
Operation (x8 Mode)
Receiver Channel
Receiver Channel
rx_out [7..0]
rx_out [3..0]
tx_outclock
rx_outclock
rx_outclock
rx_inclock
rx_inclock
Figure
tx_out
rx_in
rx_in
9–16:
3
X
7
X X X X
2
X X X X X X X
6
X X X X X X X X
1
Table 9–3
The MSB and LSB positions increase with the number of channels used in a system.
Table 9–3. Differential Bit Naming (Part 1 of 2)
5
Previous Cycle
0
4
Receiver Channel Data
X X X
3
X X X X
2
lists the conventions for differential bit naming for 18 differential channels.
Number
1
X X X
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
0
MSB
7
X X X X
X
6
X
Current Cycle
5
X X X
X X X X X X X X
X
4 3
X
3210
Chapter 9: High-Speed Differential I/O Interfaces and DPA in Stratix III Devices
X
2
X X X
X
1
LSB
X
0
X X X
X
MSB Position
Next Cycle
X
103
111
119
127
X
15
23
31
39
47
55
63
71
79
87
95
7
(Note 1)
X X X X 7 6 5 4
X X X X X
X
Internal 8-Bit Parallel Data
X
X
X
X
X
X
© July 2010 Altera Corporation
X
X
LSB Position
3 2 1 0 X X X X
X
104
112
120
16
24
32
40
48
56
64
72
80
88
96
0
8
X
X
X
Clocking
X