EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 292

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

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PLL
Stratix III Device Handbook, Volume 1
f
Programmable Slew Rate Control
Stratix III devices provide four levels of static output slew rate control: 0, 1, 2, and 3,
where 0 is the slowest slew rate setting and 3 is the fastest slew rate setting. The
default setting for the HSTL and SSTL I/O standards is 3. A fast slew rate setting
allows you to achieve higher I/O performance; a slow slew-rate setting reduces
system noise and signal overshoot. This feature is disabled if you are using the OCT
R
Programmable Drive Strength
You can choose the optimal drive strength required for your interface after
performing a board simulation. Higher drive strength helps provide a larger voltage
swing, which in turn provides bigger eye diagrams with greater timing margin.
However, higher drive strengths typically require more power, faster slew rates, and
add to simultaneous switching noise. You can use programmable slew rate control
along with this feature to minimize simultaneous switching noise with higher drive
strengths.
This feature is disabled if you use the OCT R
strength in Stratix III devices. Use the OCT R
read/write data; use the dynamic OCT setting for bi-directional data signals. You
must simulate the system to determine the drive strength required for command,
address, and clock signals.
PLLs are used to generate the memory interface controller clocks, similar to the 0°
system clock, the –90° or 270° phase-shifted write clock, the half-rate PHY clock, and
the resynchronization clock. You can use the PLL reconfiguration feature to calibrate
resynchronization phase shift to balance the setup and hold margin.
The VCO and counter setting combinations may be limited for high-performance
memory interfaces.
For more information about the Stratix III PLL, refer to the
Stratix III Devices
S
features.
chapter.
Chapter 8: External Memory Interfaces in Stratix III Devices
S
T
/R
feature, which is the default drive
S
setting for uni-directional
Stratix III External Memory Interface Features
Clock Networks and PLLs in
© March 2010 Altera Corporation