EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 221

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

Chapter 7: Stratix III Device I/O Features
Stratix III I/O Structure
Programmable Delay
Open-Drain Output
© July 2010
Altera Corporation
f
f
Table 7–6. Default Programmable Slew Rate
You can use faster slew rates to improve the available timing margin in
memory-interface applications or when the output pin has high-capacitive loading.
Altera recommends performing IBIS or SPICE simulations to determine the right slew
rate setting for your specific application.
The Stratix III device IOE includes programmable delays (refer to
can activate to ensure zero hold times, minimize setup times, or increase
clock-to-output times. Each pin can have a different input delay from pin to input
register or a delay from the output register to the output pin values to ensure that the
bus has the same delay going into or out of the device. This feature helps read and
time margins as it minimizes the uncertainties between signals in the bus.
For the programmable IOE delay specifications, refer to the
Characteristics of Stratix III Devices
Programmable Output Buffer Delay
Stratix III devices support delay chains built inside the single-ended output buffer, as
shown in
rising and falling edge delays of the output buffer, providing the ability to adjust the
output-buffer duty cycle, compensate channel-to-channel skew, reduce simultaneous
switching output (SSO) noise by deliberately introducing channel-to-channel skew,
and improve high-speed memory-interface timing margins. Stratix III devices support
four levels of output buffer delay settings. The default setting is No Delay.
For the programmable output buffer delay specifications, refer to the
Switching Characteristics of Stratix III Devices
Stratix III devices provide an optional open-drain output (equivalent to an
open-collector output) for each I/O pin. When configured as open-drain, the logic
value of the output is either high-Z or 0. Typically, an external pull-up resistor is
required to provide logic high.
1.2-V, 1.5-V, 1.8-V, 2.5-V, 3.0-V, and 3.3-V LVTTL / LVCMOS
3.0-V PCI / PCI-X
SSTL-2, -18, -15 Class I and Class II
HSTL-18, -15, -12 Class I and II
Differential SSTL-2, -18, -15 Class I and Class II
Differential HSTL-18, -15, -12 Class I and Class II
LVDS_E_1R, mini-LVDS_E_1R, RSDS_E_1R
LVDS_E_3R, mini-LVDS_E_3R, RSDS_E_3R
Figure 7–7 on page
I/O Standard
7–13. The delay chains can independently control the
chapter.
chapter.
Default Slew Rate Setting
Stratix III Device Handbook, Volume 1
DC and Switching
Figure
3
3
3
3
3
3
3
3
DC and
7–7) that you
7–17