EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 438

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

15–8
Figure 15–1. Error Detection Block Diagram
Table 15–4. Error Detection Registers (Part 1 of 2)
Stratix III Device Handbook, Volume 1
Syndrome Register
Error Message
Register
JTAG Update Register
User Update Register
Readback bit
stream with
expected CRC
included
Register
Error Injection Block
Injection Register
Fault Injection
JTAG Fault
Register
Error Detection
State Machine
Table 15–5
This register contains the CRC signature of the current frame through the error detection
verification cycle. The CRC_ERROR signal is derived from the contents of this register.
This 46-bit register contains information about the error type, location of the error, and the actual
syndrome. The types of errors and location reported are single and double adjacent bit errors. The
location bits for other types of errors are not identified by the Error Message Register. You can
shift out the content of the register through the JTAG SHIFT_EDERROR_REG instruction or to
the core through the core interface.
This register is automatically updated with the contents of the Error Message Register one cycle
after the 46-bit register content is validated. It includes a clock enable which needs to be asserted
prior to being sampled into the JTAG Shift Register. This requirement ensures that the JTAG
Update Register is not being written into by the contents of the Error Message Register at exactly
the same time that the JTAG Shift Register is reading its contents.
This register is automatically updated with the contents of the Error Message Register, one cycle
after the 46-bit register content is validated. It includes a clock enable which needs to be asserted
prior to being sampled into the User Shift Register. This requirement ensures that the User Update
Register is not being written into by the contents of the Error Message Register at exactly the
same time that the User Shift Register is reading its contents.
lists the registers shown in
Control Signals
JTAG Update
JTAG TDO
JTAG Shift
Register
Register
Calculation and Error
Error Message
16-Bit CRC
Search Engine
Register
Figure
Description
30
46
General Routing
User Update
User Shift
15–1.
Register
Register
Chapter 15: SEU Mitigation in Stratix III Devices
8
Syndrome
Register
© March 2010 Altera Corporation
16
Error Detection Block
CRC_ERROR