EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 32
![IC STRATX III FPGA 150K 1152FBGA](/photos/6/72/67293/544-1152-fbga_sml.jpg)
EP3SL150F1152C3N
Manufacturer Part Number
EP3SL150F1152C3N
Description
IC STRATX III FPGA 150K 1152FBGA
Manufacturer
Altera
Series
Stratix® IIIr
Datasheets
1.EP3SL150F780C4N.pdf
(16 pages)
2.EP3SL150F780C4N.pdf
(332 pages)
3.EP3SL150F780C4N.pdf
(456 pages)
Specifications of EP3SL150F1152C3N
Number Of Logic Elements/cells
142500
Number Of Labs/clbs
5700
Total Ram Bits
6390
Number Of I /o
744
Voltage - Supply
0.86 V ~ 1.15 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
For Use With
544-2568 - KIT DEVELOPMENT STRATIX III
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-2408
EP3SL150F1152C3NES
EP3SL150F1152C3NES
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3SL150F1152C3N
Manufacturer:
ALTERA
Quantity:
490
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1–4
Stratix III Device Handbook, Volume 1
Table 1–2
Table 1–2. Package Options and I/O Pin Counts
All Stratix III devices support vertical migration within the same package (for
example, you can migrate between the EP3SL50 and EP3SL70 devices in the 780-pin
FineLine BGA package). Vertical migration allows you to migrate to devices whose
dedicated pins, configuration pins, and power pins are the same for a given package
across device densities.
To ensure that a board layout supports migratable densities within one package
offering, enable the applicable vertical migration path within the Quartus
software. On the Assignments menu, point to Device and click Migration Devices.
You can migrate from the L family to the E family without increasing the number of
LEs available. This minimizes the cost of vertical migration.
Table 1–3
Table 1–3. FineLine BGA Package Sizes
EP3SL50
EP3SL70
EP3SL110
EP3SL150
EP3SL200
EP3SL340
EP3SE50
EP3SE80
EP3SE110
EP3SE260
Notes to
(1) The arrows indicate vertical migration.
(2) All I/O pin counts include eight dedicated clock inputs (CLK1p, CLK1n, CLK3p, CLK3n, CLK8p, CLK8n,
(3) All I/O pin counts include eight dedicated clock inputs (CLK1p, CLK1n, CLK3p, CLK3n, CLK8p,
(4) The EP3SL340 FPGA is offered only in the H1152 package, but not offered in the F1152 package.
(5) The EP3SE260 and EP3SL200 FPGAs are offered only in the H780 package, but not offered in the F780 package.
Pitch (mm)
Area (mm
Length/Width (mm/ mm)
CLK10p, and CLK10n) that can be used for data inputs.
CLK8n, CLK10p, and CLK10n) and eight dedicated corner PLL clock inputs (PLL_L1_CLKp,
PLL_L1_CLKn, PLL_L4_CLKp, PLL_L4_CLKn, PLL_R4_CLKp, PLL_R4_CLKn, PLL_R1_CLKp,
and PLL_R1_CLKn) that can be used for data inputs.
Device
Table
Dimension
2
lists the Stratix III FPGA package options and I/O pin counts.
lists the Stratix III FineLine BGA (FBGA) package sizes.
)
1–2:
FineLine
484-Pin
BGA
296
296
296
—
—
—
—
—
—
—
(2)
484 Pin
23/23
1.00
529
FineLine
780-Pin
BGA
488
488
488
488
488
488
488
488
488
—
(5)
(5)
(2)
780 Pin
29/29
1.00
841
(Note 1)
1152-Pin
FineLine
BGA
744
744
744
744
744
744
744
—
—
—
1152 Pin
(4)
Chapter 1: Stratix III Device Family Overview
(2)
35/35
1,225
1.00
FineLine BGA
© March 2010 Altera Corporation
1517-Pin
976
976
976
(3)
—
—
—
—
—
—
—
1517 Pin
1,600
40/40
1.00
Features Summary
FineLine BGA
®
1760-Pin
II
1760 Pin
1,120
1,849
43/43
(3)
—
—
—
—
—
—
—
—
—
1.00
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