EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 372

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

11–40
Table 11–12. Dedicated Configuration Pin Connections During JTAG Configuration
Stratix III Device Handbook, Volume 1
nCE
nCEO
MSEL
nCONFIG
nSTATUS
CONF_DONE
DCLK
Signal
On all Stratix III devices in the chain, nCE should be driven low by connecting it to ground, pulling it low by
using a resistor, or driving it by some control circuitry. For devices that are also in multi-device FPP, AS, or
PS configuration chains, the nCE pins should be connected to GND during JTAG configuration or JTAG
configured in the same order as the configuration chain.
On all Stratix III devices in the chain, you can leave nCEO floating or connected to the nCE of the next
device.
These pins must not be left floating. These pins support whichever non-JTAG configuration is used in
production. If you only use JTAG configuration, tie these pins to ground.
Driven high by connecting to V
Pull to V
nSTATUS pin should be pulled up to V
Pull to V
CONF_DONE pin should be pulled up to V
configuration indicates successful configuration.
Should not be left floating. Drive low or high, whichever is more convenient on your board.
Stratix III devices have dedicated JTAG pins that always function as JTAG pins. Not
only can you perform JTAG testing on Stratix III devices before and after, but also
during configuration. While other device families do not support JTAG testing during
configuration, Stratix III devices support the bypass, id code, and sample instructions
during configuration without interrupting configuration. All other JTAG instructions
may only be issued by first interrupting configuration and reprogramming I/O pins
using the CONFIG_IO instruction.
The CONFIG_IO instruction allows I/O buffers to be configured by using the JTAG
port and when issued, interrupts configuration. This instruction allows you to
perform board-level testing prior to configuring the Stratix III device or waiting for a
configuration device to complete configuration. When configuration has been
interrupted and JTAG testing is complete, you must reconfigure the part by using
JTAG (PULSE_CONFIG instruction) or by pulsing nCONFIG low.
The chip-wide reset (DEV_CLRn) and chip-wide output enable (DEV_OE) pins on
Stratix III devices do not affect JTAG boundary-scan or programming operations.
Toggling these pins does not affect JTAG operations (other than the usual
boundary-scan operation).
When designing a board for JTAG configuration of Stratix III devices, consider the
dedicated configuration pins.
during JTAG configuration.
When programming a JTAG device chain, one JTAG-compatible header is connected
to several devices. The number of devices in the JTAG chain is limited only by the
drive capability of the download cable. When four or more devices are connected in a
JTAG chain, Altera recommends buffering the TCK, TDI, and TMS pins with an
on-board buffer.
JTAG-chain device programming is ideal when the system contains multiple devices,
or when testing your system using JTAG BST circuitry.
multi-device JTAG configuration.
CC PGM
CC PGM
by using a 10-kΩ resistor. When configuring multiple devices in the same JTAG chain, each
by using a 10-kΩ resistor. When configuring multiple devices in the same JTAG chain, each
C CPGM
, pull up by using a resistor, or driven high by some control circuitry.
CC PGM
Table 11–12
CC PGM
individually.
individually. CONF_DONE going high at the end of JTAG
Description
lists how these pins should be connected
Chapter 11: Configuring Stratix III Devices
Figure 11–20
© March 2011 Altera Corporation
shows
JTAG Configuration