EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 251

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

Chapter 8: External Memory Interfaces in Stratix III Devices
Memory Interfaces Pin Support
Figure 8–2. External Memory Interface Data Path Overview
Notes to
(1) Each register block can be bypassed.
(2) The blocks for each memory interface may differ slightly.
(3) These signals may be bi-directional or uni-directional, depending on the memory standard. When bi-directional, the signal is active during both
Memory Interfaces Pin Support
© March 2010 Altera Corporation
Clock Management & Reset
read and write operations.
Figure
f
8–2:
Resynchronization
Figure 8–2
Stratix III I/O Element (IOE) features.
DQ Write Clock
Half-Rate Clock
Alignment Clock
DQS Write Clock
This chapter describes the hardware features in Stratix III devices that facilitate
high-speed memory interfacing for each DDR memory standard. Stratix III devices
feature DLLs, PLLs, dynamic OCT, read and write leveling, and deskew ciruitry.
A typical memory interface requires data (D, Q, or DQ), data strobe (DQS/CQ and
DQSn/CQn), address, command, and clock pins. Some memory interfaces use data
mask (DM) pins to enable write masking and QVLD pins to indicate that the read data
is ready to be captured. This section describes how Stratix III devices support all these
different pins.
For more information on memory interfaces, refer to the
Guidelines.
Half-Rate
Clock
shows an overview of the memory interface data path that uses all the
FIFO
(2)
4n
4
4n
Output Registers
Output Registers
Half Data Rate
Half Data Rate
Half Data Rate
Input Registers
Postamble Enable
Postamble Clock
(Note
2n
2
2n
1), (2),
Synchronization
Alignment &
Resynchronization Clock
Postamble
Alignment
Alignment
Registers
Registers
Registers
Control
Circuit
DLL
(3)
2n
2
2n
DDR Output
Registers
DDR Output
Registers
DDR Input
DQS Logic
DQS Enable
Registers
Block
Circuit
Stratix III Pin Connection
Stratix III FPGA
Stratix III Device Handbook, Volume 1
n
n
Memory
DQS (Read)
DQ (Read)
DQ (Write)
DQS (Write)
8–3