EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 89
![IC STRATX III FPGA 150K 1152FBGA](/photos/6/72/67293/544-1152-fbga_sml.jpg)
EP3SL150F1152C3N
Manufacturer Part Number
EP3SL150F1152C3N
Description
IC STRATX III FPGA 150K 1152FBGA
Manufacturer
Altera
Series
Stratix® IIIr
Datasheets
1.EP3SL150F780C4N.pdf
(16 pages)
2.EP3SL150F780C4N.pdf
(332 pages)
3.EP3SL150F780C4N.pdf
(456 pages)
Specifications of EP3SL150F1152C3N
Number Of Logic Elements/cells
142500
Number Of Labs/clbs
5700
Total Ram Bits
6390
Number Of I /o
744
Voltage - Supply
0.86 V ~ 1.15 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
For Use With
544-2568 - KIT DEVELOPMENT STRATIX III
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-2408
EP3SL150F1152C3NES
EP3SL150F1152C3NES
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3SL150F1152C3N
Manufacturer:
ALTERA
Quantity:
490
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Chapter 4: TriMatrix Embedded Memory Blocks in Stratix III Devices
Overview
Figure 4–7. Output Latch Asynchronous Clear Waveform
Error Correction Code Support
© May 2009 Altera Corporation
aclr at latch
outclk
aclr
q
f
1
1
You can selectively enable asynchronous clears per logical memory via the Quartus II
RAM MegaWizard Plug-In Manager.
For more information, refer to the
Stratix III M144K blocks have built-in support for error correction code (ECC) when in
×64-wide simple dual-port mode. ECC allows you to detect and correct data errors in
the memory array. The M144K blocks have a single-error-correction
double-error-detection (SECDED) implementation. SECDED can detect and fix a
single-bit error in a 64-bit word or detect two-bit errors in a 64-bit word. It cannot
detect three or more errors.
The M144K ECC status is communicated via a three-bit status flag
eccstatus[2..0]. The status flag can be either registered or unregistered. When
registered, it uses the same clock and asynchronous clear signals as the output
registers. When not registered, it cannot be asynchronously cleared.
Table 4–3
Table 4–3. Truth Table for ECC Status Flags
You cannot use the byte-enable feature when ECC is engaged.
Read during write “old data” mode is not supported when ECC is engaged.
No error
Single error and fixed
Double error and no fix
Illegal
Illegal
Illegal
Illegal
Status
shows the truth table for the ECC status flags.
eccstatus[2]
0
0
1
0
0
1
1
RAM Megafunction User
eccstatus[1]
0
1
0
0
1
0
1
Guide.
Stratix III Device Handbook, Volume 1
eccstatus[0]
X
0
1
1
1
0
0
4–9
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