EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 58

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

2–14
Stratix III Device Handbook, Volume 1
1
Carry Chain
The carry chain provides a fast carry function between the dedicated adders in
arithmetic or shared arithmetic mode. The two-bit carry select feature in Stratix III
devices halves the propagation delay of carry chains within the ALM. Carry chains
can begin in either the first ALM or the sixth ALM in an LAB. The final carry-out
signal is routed to a ALM, where it is fed to local, row, or column interconnects.
The Quartus II Compiler automatically creates carry chain logic during design
processing, or you can create it manually during design entry. Parameterized
functions such as LPM functions automatically take advantage of carry chains for the
appropriate functions.
The Quartus II Compiler creates carry chains longer than 20 (10 ALMs in arithmetic or
shared arithmetic mode) by linking LABs together automatically. For enhanced
fitting, a long carry chain runs vertically allowing fast horizontal connections to
TriMatrix™ memory and DSP blocks. A carry chain can continue as far as a full
column.
To avoid routing congestion in one small area of the device when a high fan-in
arithmetic function is implemented, the LAB can support carry chains that only utilize
either the top half or the bottom half of the LAB before connecting to the next LAB.
This leaves the other half of the ALMs in the LAB available for implementing
narrower fan-in functions in normal mode. Carry chains that use the top five ALMs in
the first LAB carry into the top half of the ALMs in the next LAB within the column.
Carry chains that use the bottom five ALMs in the first LAB carry into the bottom half
of the ALMs in the next LAB within the column. In every alternate LAB column, the
top half can be bypassed; in the other MLAB columns, the bottom half can be
bypassed.
For more information on carry chain interconnect, refer to
page
Shared Arithmetic Mode
In shared arithmetic mode, the ALM can implement a three-input add within an
ALM. In this mode, the ALM is configured with 4 four-input LUTs. Each LUT either
computes the sum of three inputs or the carry of three inputs. The output of the carry
computation is fed to the next adder (either to adder1 in the same ALM or to adder0
of the next ALM in the LAB) via a dedicated connection called the shared arithmetic
chain. This shared arithmetic chain can significantly improve the performance of an
adder tree by reducing the number of summation stages required to implement an
adder tree.
2–20.
Figure 2–13
shows the ALM using this feature.
Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Stratix III Devices
“ALM Interconnects” on
© February 2009 Altera Corporation
Adaptive Logic Modules