EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 102

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

4–22
Figure 4–19. Same Port Read-During-Write: New Data Mode
Note to
(1) “X” can be a don’t care value or current data at that location, depending on the setting chosen in the Quartus II software.
Figure 4–20. Same Port Read-During-Write: Old Data Mode
Note to
(1) D
Stratix III Device Handbook, Volume 1
old
Figure
Figure
is the old data bit at address
4–19:
4–20:
q_a (asyn)
q_a (asyn)
address
bytenna
address
bytenna
data_a
data_a
wrena
wrena
clk_a
rdena
clk_a
rdena
Figure 4–19
behavior with new data.
Figure 4–20
behavior with old data mode.
Mixed-Port Read-During-Write Mode
This mode applies to a RAM in simple or true dual-port mode which has one port
reading and the other port writing to the same address location with the same clock.
In this mode you also have two output choices: old data or don’t care. In old data
mode, a read-during-write operation to different ports causes the RAM outputs to
reflect the old data at that address location. In don’t care mode, the same operation
results in a “don’t care” or “unknown” value on the RAM outputs.
A0
,
A0
shows the sample functional waveforms of same-port read-during-write
shows the sample functional waveforms of same-port read-during-write
(old data) is the old data at address
A123
A123
01
01
A0 (old data)
XX23
B456
B456
10
10
0A
A0
D
old
B4XX
D
old
(Note 1)
23
C789
C789
00
(Note 1)
00
Chapter 4: TriMatrix Embedded Memory Blocks in Stratix III Devices
XXXX
B423
A0
, and
DDDD
DDDD
A1(old data)
A1
DDDD
(old data) is the old data at address
0B
EEEE
11
A1
EEEE
11
EEEE
DDDD
FFFF
FFFF
© May 2009 Altera Corporation
FFFF
EEEE
Design Considerations
A1
.