EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 119

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

Chapter 5: DSP Blocks in Stratix III Devices
DSP Block Resource Descriptions
Pipeline Register Stage
Second-Stage Adder
© March 2010 Altera Corporation
1
1
1
1
Each Half Block has its own signa and signb signal. Therefore, all of the data A
inputs feeding the same DSP Half Block must have the same sign representation.
Similarly, all of the data B inputs feeding the same DSP Half Block must have the
same sign representation. The multiplier offers full precision regardless of the sign
representation in all operational modes except for full precision 18 x 18 loopback and
Two-Multiplier Adder modes. Refer to
page 5–21
When the signa and signb signals are unused, the Quartus II software sets the
multiplier to perform unsigned multiplication by default.
The outputs of the multipliers are the only outputs that can feed into the first-stage
adder, as shown in
adders per half DSP block). The first-stage adder block has the ability to perform
addition and subtraction. The control signal for addition or subtraction is static and
has to be configured upon compile time. The first-stage adders are used by the sum
modes to compute the sum of two multipliers, 18 × 18-complex multipliers, and to
perform the first stage of a 36 × 36 multiply and shift operation.
Depending on your specifications, the output of the first-stage adder has the option to
feed into the pipeline registers, second-stage adder, round and saturation unit, or the
output registers.
The output from the first-stage adder can either feed or bypass the pipeline registers,
as shown in
performance (at the expense of extra cycles of latency), especially when using the
subsequent DSP block stages. Pipeline registers split up the long signal path between
the input-registers/multiplier/first-stage adder and the second-stage
adder/round-and-saturation/output-registers, creating two shorter paths.
There are four individual 44-bit second-stage adders per DSP block (2 adders per half
DSP block). You can configure the second-stage adders as follows:
■
■
■
■
The chained-output adder can be used at the same time as a second-level adder in
chained output summation mode.
The output of the second-stage adder has the option to go into the round and
saturation logic unit or the output register.
You cannot use the second-stage adder independently from the multiplier and
first-stage adder.
The final stage of a 36-bit multiplier
A sum of four (18 × 18)
An accumulator (44-bits maximum)
A chained output summation (44-bits maximum)
for details.
Figure
Figure
5–6. Pipeline registers increase the DSP block’s maximum
5–6. There are four first-stage adders in a DSP block (two
“Two-Multiplier Adder Sum Mode” on
Stratix III Device Handbook, Volume 1
5–13