EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 71

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

Chapter 3: MultiTrack Interconnect in Stratix III Devices
Column Interconnects
Table 3–1. Stratix III Device Routing Scheme
© October 2008 Altera Corporation
Shared
arithmetic chain
Carry chain
Register chain
Local
interconnect
Direct link
interconnect
R4 interconnect
R20
interconnect
C4 interconnect
C12 interconnect
ALM
MLAB RAM
block
M9K RAM block
M144K block
DSP blocks
Column IOE
Row IOE
Notes to
(1) Except column IOE local interconnects.
(2) Row IOE local interconnects.
(3) Column IOE local interconnects.
Source
Table
3–1:
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C12 column interconnects span a length of 12 LABs and provide the fastest resource
for column connections between distant LABs, TriMatrix memory blocks, DSP blocks,
and IOEs. C12 interconnects drive LAB local interconnects via C4 and R4
interconnects and do not drive LAB local interconnects directly.
All embedded blocks communicate with the logic array through interconnects similar
to LAB-to-LAB interfaces. Each block (for example, TriMatrix memory blocks and
DSP blocks) connects to row and column interconnects and has local interconnect
regions driven by row and column interconnects. These blocks also have direct link
interconnects for fast connections to and from a neighboring LAB.
Table 3–1
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shows the Stratix III device's routing scheme.
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Destination
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Stratix III Device Handbook, Volume 1
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