EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 46

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

2–2
Figure 2–1. Stratix III LAB Structure
Stratix III Device Handbook, Volume 1
Direct link
interconnect from
adjacent block
Direct link
interconnect to
adjacent block
R20
R4
f
The LAB of Stratix III has a new derivative called Memory LAB (MLAB), which adds
look-up table (LUT)-based SRAM capability to the LAB as shown in
MLAB supports a maximum of 320-bits of simple dual-port static random access
memory (SRAM). You can configure each ALM in an MLAB as a 16 × 2 block,
resulting in a configuration of 16 × 20 simple dual port SRAM block. MLAB and LAB
blocks always co-exist as pairs in all Stratix III families. MLAB is a superset of the LAB
and includes all LAB features.
topology.
The MLAB is described in detail in the
Devices
chapter in volume 1 of the Stratix III Device Handbook.
Local Interconnect
LAB
Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Stratix III Devices
Figure 2–2
C4
from Either Side by Columns & LABs,
C12
Local Interconnect is Driven
TriMatrix Embedded Memory Blocks in Stratix III
& from Above by Rows
shows an overview of LAB and MLAB
Row Interconnects of
Variable Speed & Length
MLAB
© February 2009 Altera Corporation
ALMs
Column Interconnects of
Variable Speed & Length
Figure
Logic Array Blocks
2–2. The
Direct link
interconnect from
adjacent block
Direct link
interconnect to
adjacent block