EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 360

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

11–28
Stratix III Device Handbook, Volume 1
1
Upon power-up, Stratix III devices go through a POR. The POR delay is dependent on
the PORSEL pin setting. When PORSEL is driven low, the POR time is approximately
100 ms. When PORSEL is driven high, the POR time is approximately 12 ms. During
POR, the device resets, holds nSTATUS low, and tri-states all user I/O pins. When the
device successfully exits POR, all user I/O pins continue to be tri-stated. If
nIO_pullup is driven low during power-up and configuration, the user I/O pins
and dual-purpose I/O pins will have weak pull-up resistors that are on (after POR)
before and during configuration. If nIO_pullup is driven high, the weak pull-up
resistors are disabled.
The configuration cycle consists of three stages: reset, configuration, and initialization.
While nCONFIG or nSTATUS are low, the device is in reset. To initiate configuration,
the MAX II device must generate a low-to-high transition on the nCONFIG pin.
V
reside must be fully powered to the appropriate voltage levels to begin the
configuration process.
When nCONFIG goes high, the device comes out of reset and releases the open-drain
nSTATUS pin, which is then pulled high by an external 10-kΩ pull-up resistor. When
nSTATUS is released, the device is ready to receive configuration data and the
configuration stage begins. When nSTATUS is pulled high, the MAX II device should
place the configuration data one bit at a time on the DATA0 pin. If you are using
configuration data in .rbf, .hex, or .ttf format, you must send the least significant bit
(LSB) of each data byte first. For example, if the RBF contains the byte sequence 02
1B EE 01 FA, the serial bitstream you must transmit to the device is 0100-0000
1101-1000 0111-0111 1000-0000 0101-1111.
The Stratix III device receives configuration data on the DATA0 pin and the clock is
received on the DCLK pin. Data is latched into the device on the rising edge of DCLK.
Data is continuously clocked into the target device until CONF_DONE goes high. After
the device has received all configuration data successfully, it releases the open-drain
CONF_DONE pin, which is pulled high by an external 10-kΩ pull-up resistor. A
low-to-high transition on CONF_DONE indicates configuration is complete and
initialization of the device can begin. The CONF_DONE pin must have an external
10-kΩ pull-up resistor for the device to initialize.
In Stratix III devices, the initialization clock source is either the internal oscillator
(typically 10 MHz) or the optional CLKUSR pin. By default, the internal oscillator is
the clock source for initialization. If you use the internal oscillator, the Stratix III
device has enough clock cycles for proper initialization. Therefore, if the internal
oscillator is the initialization clock source, sending the entire configuration file to the
device is sufficient to configure and initialize the device. Driving DCLK to the device
after configuration is complete does not affect device operation.
You also have the flexibility to synchronize initialization of multiple devices or to
delay initialization with the CLKUSR option. You can turn on the Enable
user-supplied start-up clock (CLKUSR) option in the Quartus II software on the
General tab of the Device and Pin Options dialog box. If you supply a clock on
CLKUSR, it will not affect the configuration process. After all configuration data has
been accepted and CONF_DONE goes high, CLKUSR will be enabled after the time
specified as t
cycles to initialize properly and enter user mode. Stratix III devices support a CLKUSR
f
MAX
CC
, V
of 100 MHz.
CCIO
, V
CCPGM
CD2CU
, and V
. After this time period elapses, Stratix III devices require 4,436 clock
CCPD
of the banks where the configuration and JTAG pins
Chapter 11: Configuring Stratix III Devices
© March 2011 Altera Corporation
Passive Serial Configuration