EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 243

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

Chapter 7: Stratix III Device I/O Features
Design Considerations
Figure 7–28. Mini-LVDS I/O Standard Termination for Stratix III Devices
Notes to
(1) R
(2) Column and row I/O banks support mini-LVDS_E_1R and mini-LVDS_E_3R I/O standards using two single-ended output buffers.
Design Considerations
© July 2010
Termination
Termination
On-Board
External
OCT
P
=120 Ω for mini-LVDS_E_1R, R
Figure
Altera Corporation
f
7–28:
Transmitter
Transmitter
A resistor network is required to attenuate the LVDS output voltage swing to meet the
mini-LVDS specifications. You can modify the three-resistor network values to reduce
power or improve the noise margin. The resistor values chosen should satisfy
Equation
Equation 7–2.
Altera recommends that you perform additional simulations using IBIS models to
validate that custom resistor values meet the RSDS requirements.
For more information about the mini-LVDS I/O standard, refer to the mini-LVDS
Specification from the
While Stratix III devices feature various I/O capabilities for high-performance and
high-speed system designs, there are several other considerations that require
attention to ensure the success of those designs.
One-Resistor Network (mini-LVDS_E_1R)
≤1 inch
≤1 inch
P
=170 Ω , and R
R
R
P
7–2:
P
50 Ω
50 Ω
50 Ω
50 Ω
100 Ω
S
=120 Ω for mini-LVDS_E_3R.
Texas Instruments
100 Ω
Stratix III OCT
Receiver
Receiver
Rs
------------------- -
Rs
×
+
website.
Rp
----- -
Rp
----- -
2
2
Transmitter
Transmitter
(Note
=
50Ω
1),
Three-Resistor Network (mini-LVDS_E_3R)
(2)
R S
R S
≤1 inch
≤
R S
R S
1 inch
R
P
R
P
Stratix III Device Handbook, Volume 1
50 Ω
50 Ω
50 Ω
50 Ω
100 Ω
100
Ω
Stratix III OCT
Receiver
Receiver
7–39