EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 183

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

Chapter 6: Clock Networks and PLLs in Stratix III Devices
PLLs in Stratix III Devices
Figure 6–33. Automatic Switchover Upon Loss of Clock Detection
Note to
(1) Switchover is enabled on the falling edge of
© July 2010
the falling edge of
Figure
Altera Corporation
6–33:
1
inclk1.
When using the automatic clock switchover mode, the following requirements must
be satisfied:
■
■
If the current clock input stops toggling while the other clock is also not toggling,
switchover will not be initiated and the clkbad[0..1] signals will not be valid.
Also, if both clock inputs are not the same frequency, but their period difference is
within 100%, the clock sense block will detect when a clock stops toggling, but the
PLL may lose lock after the switchover is completed and need time to re-lock.
Altera recommends resetting the PLL using the areset signal to maintain the phase
relationships between the PLL input and output clocks when using clock switchover.
When using automatic switchover mode, the clkbad[0] and clkbad[1] signals
indicate the status of the two clock inputs. When they are asserted, the clock sense
block has detected that the corresponding clock input has stopped toggling. These
two signals are not valid if the frequency difference between inclk0 and inclk1 is
greater than 20%.
The activeclock signal indicates which of the two clock inputs (inclk0 or
inclk1) is being selected as the reference clock to the PLL. When the frequency
difference between the two clock inputs is more than 20%, the activeclock signal is
the only valid status signal.
Figure 6–33
automatic switchover mode. In this example, the inclk0 signal remains low. After
the inclk0 signal remains low for approximately two clock cycles, the clock sense
circuitry drives the clkbad[0] signal high. Also, because the reference clock signal is
not toggling, the switchover state machine controls the multiplexer through the
clksw signal to switch to the backup clock, inclk1.
Both clock inputs must be running.
The period of the two clock inputs can differ by no more than 100% (2×).
activeclock
clkbad0
clkbad1
muxout
inclk0
inclk1
shows an example waveform of the switchover feature when using the
inclk0 or inclk1
,
depending on which clock is available. In this figure, switchover is enabled on
(1)
Stratix III Device Handbook, Volume 1
6–35