EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 246

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

7–42
Chapter Revision History
Table 7–13. Chapter Revision History (Part 1 of 2)
Stratix III Device Handbook, Volume 1
July 2010
March 2010
May 2009
February 2009
October 2008
Date and Revision
Table 7–13
Version
1.9
1.8
1.7
1.6
1.5
lists the revision history for this chapter.
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Updated for the Quartus II software version 9.1 SP2 release:
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Text, Table, and Figure updates:
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Updated
Updated
Updated “Programmable Pull-Up Resistor” section.
Updated Figure 7–2, Figure 7–3, Figure 7–4, Figure 7–5, Figure 7–6.
Updated Table 7–2, Table 7–3, and Table 7–7.
Added reference before Table 7–11.
Removed “Conclusion” section.
Minor text edit.
Updated “Expanded On-Chip Series Termination with Calibration” and
“Mixing Voltage-Referenced and Non-Voltage-Referenced Standards”
sections.
Added “Left Shift Series Termination Control” section.
Updated Table 7–8 and Table 7–9.
Updated Figure 7–24.
Updated Table 7–3, Table 7–7, Table 7–8, and Table 7–11.
Updated Figure 7–2, Figure 7–3, Figure 7–4, Figure 7–5, and Figure 7–6.
Updated “LVDS Input On-Chip Termination (R
Removed “Referenced Documents” section.
Updated Table 7–2, Table 7–4, Table 7–7, and Table 7–10.
Updated notes for Table 7–2.
Updated notes for Figure 7–3, Figure 7–4, Figure 7–5, Figure 7–6, and
Figure 7–7.
Updated “Stratix III I/O Banks”, “Modular I/O Banks”, “High-Speed
Differential I/O with DPA Support”, “Dynamic On-Chip Termination”,
“LVDS Input On-Chip Termination (RD)”, “Serial Data Transfer”, “LVDS”,
“RSDS”, “mini-LVDS”, “Voltage-Referenced Standards”, “Stratix III I/O
Banks”, “MultiVolt I/O Interface”, and “On-Chip Parallel Termination with
Calibration” sections.
Updated Figure 7–1.
Added Table 7–3.
Updated New Document Format.
Figure
Equation 7–1
7–25,
Figure
and
Changes Made
Equation
7–26, and
7–2.
Chapter 7: Stratix III Device I/O Features
Figure
© July 2010 Altera Corporation
D
7–28.
)” section.
Chapter Revision History