EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 271
![IC STRATX III FPGA 150K 1152FBGA](/photos/6/72/67293/544-1152-fbga_sml.jpg)
EP3SL150F1152C3N
Manufacturer Part Number
EP3SL150F1152C3N
Description
IC STRATX III FPGA 150K 1152FBGA
Manufacturer
Altera
Series
Stratix® IIIr
Datasheets
1.EP3SL150F780C4N.pdf
(16 pages)
2.EP3SL150F780C4N.pdf
(332 pages)
3.EP3SL150F780C4N.pdf
(456 pages)
Specifications of EP3SL150F1152C3N
Number Of Logic Elements/cells
142500
Number Of Labs/clbs
5700
Total Ram Bits
6390
Number Of I /o
744
Voltage - Supply
0.86 V ~ 1.15 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
For Use With
544-2568 - KIT DEVELOPMENT STRATIX III
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-2408
EP3SL150F1152C3NES
EP3SL150F1152C3NES
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3SL150F1152C3N
Manufacturer:
ALTERA
Quantity:
490
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Chapter 8: External Memory Interfaces in Stratix III Devices
Stratix III External Memory Interface Features
© March 2010 Altera Corporation
Table 8–5. DLL Location and Supported I/O Banks
The reference clock for each DLL may come from PLL output clocks or any of the two
dedicated clock input pins located in either side of the DLL.
Table 8–9
device family.
When you have a dedicated PLL that only generates the DLL input reference clock, set
the PLL mode to No Compensation, or the Quartus II software changes it
automatically. As the PLL does not use any other outputs, it does not require to
compensate for any clock paths.
Table 8–6. DLL Reference Clock Input for EP3SE50, EP3SL50, and EP3SL70 Devices
DLL0
DLL1
DLL2
DLL3
DLL0
DLL1
DLL2
DLL3
1
DLL
DLL
lists the available DLL reference clock input resources for the Stratix III
You can only have one memory interface in each I/O sub-bank (such as I/O
sub-banks 1A, 1B, and 1C) when you use leveling delay chains. This is
because there is only one leveling delay chain per I/O sub-bank.
Top left corner
Bottom left corner
Bottom right corner
Top right corner
Location
(Top/Bottom)
CLK12P
CLK13P
CLK14P
CLK15P
CLK12P
CLK13P
CLK14P
CLK15P
CLK4P
CLK5P
CLK6P
CLK7P
CLK4P
CLK5P
CLK6P
CLK7P
CLKIN
1A, 1B, 1C, 2A, 2B, 2C, 7A, 7B, 7C, 8A, 8B, 8C
1A, 1B, 1C, 2A, 2B, 2C, 3A, 3B, 3C, 4A, 4B, 4C
3A, 3B, 3C, 4A, 4B, 4C, 5A, 5B, 5C, 6A, 6B, 6C
5A, 5B, 5C, 6A, 6B, 6C, 7A, 7B, 7C, 8A, 8B, 8C
(Left/Right)
CLK10P
CLK11P
CLK10P
CLK11P
CLK0P
CLK1P
CLK2P
CLK3P
CLK0P
CLK1P
CLK2P
CLK3P
CLK8P
CLK9P
CLK8P
CLK9P
CLKIN
Accessible I/O Banks
PLL (Top/Bottom)
PLL_T1
PLL_B1
PLL_B1
PLL_T1
Stratix III Device Handbook, Volume 1
Table 8–6
through
PLL (Left/Right)
PLL_R2
PLL_R2
PLL_L2
PLL_L2
8–23
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