EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 401
EP3SL150F1152C3N
Manufacturer Part Number
EP3SL150F1152C3N
Description
IC STRATX III FPGA 150K 1152FBGA
Manufacturer
Altera
Series
Stratix® IIIr
Datasheets
1.EP3SL150F780C4N.pdf
(16 pages)
2.EP3SL150F780C4N.pdf
(332 pages)
3.EP3SL150F780C4N.pdf
(456 pages)
Specifications of EP3SL150F1152C3N
Number Of Logic Elements/cells
142500
Number Of Labs/clbs
5700
Total Ram Bits
6390
Number Of I /o
744
Voltage - Supply
0.86 V ~ 1.15 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
For Use With
544-2568 - KIT DEVELOPMENT STRATIX III
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-2408
EP3SL150F1152C3NES
EP3SL150F1152C3NES
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3SL150F1152C3N
Manufacturer:
ALTERA
Quantity:
490
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Chapter 13: IEEE 1149.1 (JTAG) Boundary-Scan Testing in Stratix III Devices
IEEE Std. 1149.1 BST Architecture
Figure 13–2. IEEE Std. 1149.1 Circuitry
Note to
(1) For register lengths, refer to the device datasheet in the
© July 2010
Figure
TRST
TCLK
TMS
TDI
Altera Corporation
13–2:
Controller
TAP
Figure 13–2
IEEE Std. 1149.1 boundary-scan testing is controlled by a TAP controller. For more
information about the TAP controller, refer to
Control” on page
and TDO pins provide the serial path for the data registers. The TDI pin also provides
data to the instruction register, which then generates control logic for the data
registers.
UPDATEIR
UPDATEDR
CLOCKIR
CLOCKDR
SHIFTIR
SHIFTDR
shows a functional model of the IEEE Std. 1149.1 circuitry.
13–7. The TMS and TCK pins operate the TAP controller. The TDI
Data Registers
Instruction Register
Configuring Stratix III Devices
Bypass Register
Boundary-Scan Register
Device ID Register
ICR Registers
Instruction Decode
a
(1)
(1)
chapter in volume 1 of the Stratix III Device Handbook.
“IEEE Std. 1149.1 BST Operation
Stratix III Device Handbook, Volume 1
TDO
13–3
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