EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 234

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

7–30
Stratix III Device Handbook, Volume 1
1
User Mode
During user mode, OCTUSRCLK, ENAOCT, nCLRUSR, and ENASER[9..0] signals are
used to calibrate and serially transfer calibrated codes from each OCT calibration
block to any I/O.
and their descriptions.
Table 7–12. OCT Calibration Block Ports for User Control and Description
Figure 7–17
blocks are in calibration mode, and when ENAOCT is 0, all OCT calibration blocks are
in serial data transfer mode. The OCTUSRCLK clock frequency must be 20 MHz or less.
You must generate all user signals on the rising edge of OCTUSRCLK.
Figure 7–17. Signals Used for User Mode Calibration
Note to
(1)
OCTUSRCLK
ENAOCT
ENASER[9..0]
S2PENA_<bank#>
nCLRUSR
Figure 7–17
representation only.
Figure
Signal Name
7–17:
shows the flow of the user signal. When ENAOCT is 1, all OCT calibration
is a top view of the silicon die that corresponds to a reverse view for flip chip packages. It is a graphical
Bank 1A
Bank 1B
Bank 1C
Bank 2C
Bank 2B
Bank 2A
Table 7–12
CB1
CB0
CB9
CB2
lists the user controlled calibration block signal names
Clock for OCT block.
Enable OCT Termination (generated by user IP).
When ENAOCT = 0, each signal enables the OCT serializer for the
corresponding OCT calibration block.
When ENAOCT = 1, each signal enables OCT calibration for the
corresponding OCT calibration block.
Serial-to-parallel load enable per I/O bank.
Clear user.
S2PENA_1C
OCTUSRCLK,
ENASER[N]
CB8
CB3
ENAOCT, nCLRUSR,
Stratix III
Core
S2PENA_4C
(Note 1)
S2PENA_6C
Description
CB4
CB7
Chapter 7: Stratix III Device I/O Features
CB6
CB5
Bank 6A
Bank 6B
Bank 6C
Bank 5C
Bank 5B
Bank 5A
© July 2010 Altera Corporation
OCT Calibration