EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 77
![IC STRATX III FPGA 150K 1152FBGA](/photos/6/72/67293/544-1152-fbga_sml.jpg)
EP3SL150F1152C3N
Manufacturer Part Number
EP3SL150F1152C3N
Description
IC STRATX III FPGA 150K 1152FBGA
Manufacturer
Altera
Series
Stratix® IIIr
Datasheets
1.EP3SL150F780C4N.pdf
(16 pages)
2.EP3SL150F780C4N.pdf
(332 pages)
3.EP3SL150F780C4N.pdf
(456 pages)
Specifications of EP3SL150F1152C3N
Number Of Logic Elements/cells
142500
Number Of Labs/clbs
5700
Total Ram Bits
6390
Number Of I /o
744
Voltage - Supply
0.86 V ~ 1.15 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
For Use With
544-2568 - KIT DEVELOPMENT STRATIX III
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-2408
EP3SL150F1152C3NES
EP3SL150F1152C3NES
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3SL150F1152C3N
Manufacturer:
ALTERA
Quantity:
490
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Chapter 3: MultiTrack Interconnect in Stratix III Devices
I/O Block Connections to Interconnect
Figure 3–8. Detailed View, DSP Block Interface to Interconnect
I/O Block Connections to Interconnect
© October 2008 Altera Corporation
C4 Interconnects
LAB
18
The IOEs are located in I/O blocks around the periphery of the Stratix III device.
There are up to four IOEs per row I/O block and four IOEs per column I/O block. The
row I/O blocks drive row, column, or direct link interconnects. The column I/O
blocks drive column interconnects.
the logic array.
DSP Block to
LAB Row Interface
Block Interconnect Region
Direct Link Interconnect
from Adjacent LAB
36
20
Figure 3–10
Row Interface
72
12
Block
72 Inputs per Row
shows how a column I/O block connects to the logic array.
R4 Interconnects
20
Control
A[35..0]
B[35..0]
DSP Block
Row Structure
Figure 3–9
OA[17..0]
OB[17..0]
shows how a row I/O block connects to
36 Outputs per Row
Direct Link Outputs
to Adjacent LABs
36
36
Stratix III Device Handbook, Volume 1
Direct Link Interconnect
from Adjacent LAB
LAB
3–11
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