EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 188

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

6–40
Stratix III Device Handbook, Volume 1
A high-bandwidth PLL provides a fast lock time and tracks jitter on the reference
clock source, passing it through to the PLL output. A low-bandwidth PLL filters out
reference clock jitter but increases lock time. Stratix III PLLs allow you to control the
bandwidth over a finite range to customize the PLL characteristics for a particular
application. The programmable bandwidth feature in Stratix III PLLs benefits
applications requiring clock switchover.
A high-bandwidth PLL can benefit a system that needs to accept a spread-spectrum
clock signal. Stratix III PLLs can track a spread-spectrum clock by using a
high-bandwidth setting. Using a low-bandwidth in this case could cause the PLL to
filter out the jitter on the input clock.
A low-bandwidth PLL can benefit a system using clock switchover. When the clock
switchover happens, the PLL input temporarily stops. A low-bandwidth PLL reacts
more slowly to changes on its input clock and takes longer to drift to a lower
frequency (caused by the input stopping) than a high-bandwidth PLL.
Implementation
Traditionally, external components such as the VCO or loop filter control a PLL's
bandwidth. Most loop filters consist of passive components such as resistors and
capacitors that take up unnecessary board space and increase cost. With Stratix III
PLLs, all the components are contained within the device to increase performance and
decrease cost.
When you specify the bandwidth setting (low, medium, or high) in the ALTPLL
MegaWizard Plug-in Manager, the Quartus II software automatically sets the
corresponding charge pump and loop filter (I
bandwidth range.
Figure 6–38
Quartus II software. The components are the loop filter resistor, R, the high frequency
capacitor, C
Figure 6–38. Loop Filter Programmable Components
H
shows the loop filter and the components that you can set using the
, and the charge pump current, I
PFD
Chapter 6: Clock Networks and PLLs in Stratix III Devices
UP
cp
I
I
UP
DN
, R, C) values to achieve the desired
or I
DN
.
R
C
© July 2010 Altera Corporation
PLLs in Stratix III Devices
C
h