EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 109
EP3SL150F1152C3N
Manufacturer Part Number
EP3SL150F1152C3N
Description
IC STRATX III FPGA 150K 1152FBGA
Manufacturer
Altera
Series
Stratix® IIIr
Datasheets
1.EP3SL150F780C4N.pdf
(16 pages)
2.EP3SL150F780C4N.pdf
(332 pages)
3.EP3SL150F780C4N.pdf
(456 pages)
Specifications of EP3SL150F1152C3N
Number Of Logic Elements/cells
142500
Number Of Labs/clbs
5700
Total Ram Bits
6390
Number Of I /o
744
Voltage - Supply
0.86 V ~ 1.15 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
For Use With
544-2568 - KIT DEVELOPMENT STRATIX III
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-2408
EP3SL150F1152C3NES
EP3SL150F1152C3NES
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3SL150F1152C3N
Manufacturer:
ALTERA
Quantity:
490
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Chapter 5: DSP Blocks in Stratix III Devices
Simplified DSP Operation
Figure 5–1. Overview of DSP Block Signals
Simplified DSP Operation
Figure 5–2. Basic Two-Multiplier Adder Building Block
© March 2010 Altera Corporation
Control
Input
Data
In Stratix and Stratix II devices, the fundamental building block consists of an 18-bit ×
18-bit multiplier that can also function as two 9-bit × 9-bit multipliers. For Stratix III,
the fundamental building block is a pair of 18-bit × 18-bit multipliers followed by a
first-stage 37-bit addition/subtraction unit, as shown in
Note that for all signed numbers, input and output data is represented in 2’s
complement format only.
Equation 5–1. Multiplier Equation
A0[17..0]
B0[17..0]
A1[17..0]
B1[17..0]
288
144
144
34
D
D
Full DSP Block
Q
Q
P[36..0] = A
0
Half-DSP Block
Half-DSP Block
[17..0] × B
0
[17..0] ± A
+/−
1
[17..0] × B
Equation 5–1
72
72
Stratix III Device Handbook, Volume 1
1
P[36..0]
[17..0]
Output
Data
Output
Data
and
Figure
5–2.
5–3
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