EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 110
![IC STRATX III FPGA 150K 1152FBGA](/photos/6/72/67293/544-1152-fbga_sml.jpg)
EP3SL150F1152C3N
Manufacturer Part Number
EP3SL150F1152C3N
Description
IC STRATX III FPGA 150K 1152FBGA
Manufacturer
Altera
Series
Stratix® IIIr
Datasheets
1.EP3SL150F780C4N.pdf
(16 pages)
2.EP3SL150F780C4N.pdf
(332 pages)
3.EP3SL150F780C4N.pdf
(456 pages)
Specifications of EP3SL150F1152C3N
Number Of Logic Elements/cells
142500
Number Of Labs/clbs
5700
Total Ram Bits
6390
Number Of I /o
744
Voltage - Supply
0.86 V ~ 1.15 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
For Use With
544-2568 - KIT DEVELOPMENT STRATIX III
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-2408
EP3SL150F1152C3NES
EP3SL150F1152C3NES
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3SL150F1152C3N
Manufacturer:
ALTERA
Quantity:
490
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5–4
Stratix III Device Handbook, Volume 1
The structure shown in
structures, such as complex multipliers and 36 × 36 multipliers, as described in later
sections.
Each Stratix III DSP block contains four Two-Multiplier Adder units (two
Two-Multiplier Adder units per half-block). Therefore, there are eight 18 × 18
multiplier functionalities per DSP block.
Following the Two-Multiplier Adder units are the pipeline registers, the second-stage
adders, and an output register stage. You can configure the second-stage adders to
provide the following alternative functions per Half-Block:
Equation 5–2. Four-Multiplier Adder Equation
Equation 5–3. Four-Multiplier Adder Equation (44-Bit Accumulation)
In these equations, n denotes sample time, and P[36..0] are the results from the
Two-Multiplier Adder units.
Equation 5–2
(Four-Multiplier Adder), and
multiplication operation but with maximum of a 44-bit accumulation capability by
feeding the output of the unit back to itself. This is shown in
You can bypass all register stages depending on which mode you select.
provides a sum of four 18-bit × 18-bit multiplication operations
Figure 5–2
W
Equation 5–3
n
Z[37..0] = P
[43..0] = W
is very useful for building more complex
0
n-1
[36..0] + P
[43..0] ± Z
provides a four 18-bit × 18-bit
1
[36..0]
n
[37..0]
Chapter 5: DSP Blocks in Stratix III Devices
© March 2010 Altera Corporation
Figure
Simplified DSP Operation
5–3.
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