EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 328

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

10–4
Power-On Reset Circuitry
Stratix III Device Handbook, Volume 1
1
1
Figure 10–2
This design prevents leakage current from I/O pins to the V
powered before the other voltage supplies or if the I/O pad voltage is higher than
V
leakage current charges the 3.3-V tolerant circuit capacitance.
Figure 10–2. Transistor Level Diagram of a Stratix III Device I/O Buffers
Notes to
(1) This is the logic array signal or the larger of either the V
(2) This is the larger of either the V
When power is applied to a Stratix III device, a POR event occurs when all the power
supplies reach the recommended operating range within a certain period of time
(specified as a maximum power supply ramp time; t
Stratix III allows the required power supplies to be powered up in any sequence and
at any time between them with each individual power supply must reach the
recommended operating range within t
For maximum power supplies ramp-up time for Stratix III Devices, refer
Stratix III devices provide a dedicated input pin (PORSEL) to select a POR delay time
during power up. When the PORSEL pin is connected to ground, the POR delay time
is 100 ms. When the PORSEL pin is set to high, the POR delay time is 12 ms.
The POR block consists of a regulator POR, satellite POR, and main POR to check the
power supply levels for proper device configuration. The satellite POR monitors V
and V
programming. The POR block also checks for functionality of I/O level shifters
powered by V
and V
used during device configuration, is checked by the regulator POR block and is gated
in the main POR block for the final POR trip. A simplified block diagram of the POR
block is shown in
All configuration-related dedicated and dual function I/O pins must be powered by
V
CCIO
CCPGM
. This also applies for sudden voltage spikes during hot insertion. The V
CCPGM
CCL
.
Figure
supplies used in core. The internal configuration memory supply, which is
power supplies that are used in the configuration buffers for device
shows a transistor-level cross section of the Stratix III device I/O buffers.
10–2:
CCPD
Figure
and V
n+
Logic Array
p-well
Signal
CCPGM
10–3.
CCIO
or V
during power-up mode. The main POR checks the V
n+
PAD
signal.
Chapter 10: Hot Socketing and Power-On Reset in Stratix III Devices
V
PAD
RAMP
.
CCIO
p+
or V
PAD
(1)
signal.
RAMP
). Hot socketing feature in
n-well
V
CCIO
p+
CCIO
© March 2010 Altera Corporation
supply when V
(2)
n+
Power-On Reset Circuitry
p-substrate
Table
PAD
10–1.
CCIO
CCPD
CC
is