EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 261
![IC STRATX III FPGA 150K 1152FBGA](/photos/6/72/67293/544-1152-fbga_sml.jpg)
EP3SL150F1152C3N
Manufacturer Part Number
EP3SL150F1152C3N
Description
IC STRATX III FPGA 150K 1152FBGA
Manufacturer
Altera
Series
Stratix® IIIr
Datasheets
1.EP3SL150F780C4N.pdf
(16 pages)
2.EP3SL150F780C4N.pdf
(332 pages)
3.EP3SL150F780C4N.pdf
(456 pages)
Specifications of EP3SL150F1152C3N
Number Of Logic Elements/cells
142500
Number Of Labs/clbs
5700
Total Ram Bits
6390
Number Of I /o
744
Voltage - Supply
0.86 V ~ 1.15 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
For Use With
544-2568 - KIT DEVELOPMENT STRATIX III
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-2408
EP3SL150F1152C3NES
EP3SL150F1152C3NES
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3SL150F1152C3N
Manufacturer:
ALTERA
Quantity:
490
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Chapter 8: External Memory Interfaces in Stratix III Devices
Memory Interfaces Pin Support
© March 2010 Altera Corporation
The DQS and DQSn pins are listed in the Stratix III pin tables as
DQSXY and DQSnXY, respectively, where X denotes the DQS/DQ grouping number,
and Y denotes whether the group is located on the top (T), bottom (B), left (L), or right
(R) side of the device.
The corresponding DQ pins are marked as DQXY, where X indicates which DQS
group the pins belong to and Y indicates whether the group is located on the top (T),
bottom (B), left (L), or right (R) side of the device. For example, DQS1L indicates a
DQS pin, located on the left side of the device. Refer to
The DQ pins belonging to that group are shown as DQ1L in the pin table.
The numbering scheme starts from the top-left side of the device going
counter-clockwise.
package bottom view of the device. The top and bottom sides of the device can
contain up to 44 ×4 DQS/DQ groups. The left and right sides of the device can contain
up to 40 ×4 DQS/DQ groups.
The parity, DM, BWSn, NWSn, ECC, and QVLD pins are shown as DQ pins in the pin
table. When not used as memory interface pins, these pins are available as regular I/O
pins.
Figure 8–8
shows how the DQS/DQ groups are numbered in a
Figure 8–8
Stratix III Device Handbook, Volume 1
for an illustration.
8–13
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