EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 446

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

16–2
Programmable Power Technology
Stratix III Device Handbook, Volume 1
f
f
Lowering the core voltage reduces both static and dynamic power, but causes a
reduction in performance. You need to set the correct core supply voltage in the
Quartus II software settings under Operating Conditions, since the Quartus II
software analyzes the core power consumption and timing delays based on this
selection. When you compile a design, you can select either 0.9-V or 1.1-V core
voltage. You can compare the power and performance trade-offs of a 0.9-V core
voltage compilation result and a 1.1-V core voltage compilation result and then
choose the most desirable core voltage for your design. By default, the Quartus II
software sets the core voltage to 1.1 V.
Ensure that the board has a separate 0.9-V power supply to utilize the lower voltage
option and be sure to connect V
software. The Stratix III device cannot distinguish which core voltage level is used on
the board. Connecting to the wrong voltage level gives you different timing delays
and power consumption than what is reported by the Quartus II software.
For information about selectable core voltage performance and power effects on
sample designs, refer to
In addition to the variable core voltage, Stratix III devices also offer the ability to
configure portions of the core, called tiles, for high-speed or low-power mode of
operation performed by the Quartus II software without user intervention. This
programmable power technology, used to reduce static power, uses an on-chip
voltage regulator powered by V
determines whether a tile needs to be in high-speed or low-power mode based on the
timing constraints of the design.
For more information about how the Quartus II software uses programmable power
technology when compiling a design, refer to
A Stratix III tile can consist of the following:
■
■
■
■
■
All blocks and routing associated with the tile share the same setting of either high
speed or low power. Tiles that include DSP blocks, memory blocks, or I/O interfaces
are set to high-speed mode by default for optimum performance when used in the
design. Unused DSP blocks, memory blocks, and I/O elements are set to low-power
mode to minimize static power. Clock networks do not support programmable power
technology.
MLAB/LAB pairs with routing to the pair
MLAB/LAB pairs with routing to the pair and to adjacent DSP/memory block
routing
TriMatrix memory blocks
DSP blocks
I/O interfaces
Chapter 16: Programmable Power and Temperature-Sensing Diodes in Stratix III Devices
AN 437: Power Optimization
CCL
CCPT
to the voltage level that you set in the Quartus II
. In a design compilation, the Quartus II software
AN 437: Power Optimization
Techniques.
© February 2009 Altera Corporation
Stratix III Power Technology
Techniques.