EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 288

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

8–40
Figure 8–23. Delay Chains in an I/O Block
Figure 8–24. Delay Chains in the DQS Input Path
Stratix III Device Handbook, Volume 1
octdelaysetting2 (only)
octdelaysetting1 (only)
Figure 8–23
Each DQS logic block contains a delay chain after the dqsbusout output and another
delay chain before the dqsenable input.
DQS input path.
DQS
shows the delay chains in an I/O block.
rtena
D5 OCT
Delay
Chain
D6 OCT
Delay
Chain
Chain
(outputdelaysetting2 + outputfinedelaysetting2) or
(outputonlydelaysetting2 + outputonlyfinedelaysetting2)
DQS
Delay
D5 Output-
Enable Delay
Chain
D6 Output-
Enable Delay
Chain
(dqsenabledelaysetting +
dqsenablefinedelaysetting)
oe
(dqsbusoutdelaysetting +
dqsbusoutfinedelaysetting)
(padtoinputregisterdelaysetting +
padtoinputregisterfinedelaysetting)
D6 Delay
Delay
Chain
D4 Delay
Chain
(outputdelaysetting2 +
outputfinedelaysetting2)
D1 Delay
Delay Chain
Chapter 8: External Memory Interfaces in Stratix III Devices
Figure 8–24
(outputdelaysetting1 +
outputfinedelaysetting1)
D5 Delay
Delay
Chain
dqsin
dqsenable
Enable
Control
Enable
DQS
T11 Delay
Chain
DQS
Stratix III External Memory Interface Features
shows the delay chains in the
0
1
dqsbusout
© March 2010 Altera Corporation