EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 236

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

7–32
Figure 7–19. OCT User-Mode Signal Timing Waveform for Two OCT Blocks
Notes to
(1) ts2p ≥ 25 ns
(2) S2PENA_1A is asserted in Bank 1A for calibration block 0.
(3) S2PENA_2A is asserted in Bank 2A for calibration block 1.
Termination Schemes for I/O Standards
Single-Ended I/O Standards Termination
Stratix III Device Handbook, Volume 1
Figure
S2PENA_1A (2)
S2PENA_2A (3)
OCTUSRCLK
f
7–19:
ENASER0
ENASER1
nCLRUSR
1
ENAOCT
RS Calibration
If only RS calibration is used for an OCT calibration block, its corresponding ENASER
signal must be asserted for 240 OCTUSRCLK cycles for calibration.
You still have to assert the ENASER signal for 28 OCTUSRCLK cycles for serial transfer.
For more information, refer to the
Implementing OCT Calibration in Stratix III
The following section describes the different termination schemes for the I/O
standards used in Stratix III devices.
Voltage-referenced I/O standards require both an input reference voltage, V
termination voltage (V
termination voltage of the transmitting device.
details of SSTL and HSTL I/O termination on Stratix III devices.
1000
CY CLE S
OCTUSRCLK
Calibration Phase
1000
TT
CY CLE S
). The reference voltage of the receiving device tracks the
OCTUSRCLK
ALT_OCT Megafunction User Guide
28
Devices.
OCTUSRCLK
CY CLE S
Figure 7–20
ts2p (1)
Chapter 7: Stratix III Device I/O Features
28
Termination Schemes for I/O Standards
OCTUSRCLK
CY CLE S
and
© July 2010 Altera Corporation
Figure 7–21
and
ts2p (1)
AN 465:
REF
show the
, and a