EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 218

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

7–14
3.3-V I/O Interface
External Memory Interfaces
Stratix III Device Handbook, Volume 1
f
Stratix III I/O buffers are fully compatible with 3.3-V I/O standards, and you can use
them as transmitters or receivers in your system. The output high voltage (V
output low voltage (V
meet the 3.3-V I/O standards specifications defined by EIA/JEDEC Standard JESD8-B
with margin when the Stratix III V
For device reliability and proper operation when interfacing with a 3.3 V I/O system
using Stratix III devices, ensure that the absolute maximum ratings of Stratix III
devices are not violated. Altera recommends performing IBIS simulation to determine
that the overshoot and undershoot voltages are within the guidelines.
When using a Stratix III device as a transmitter, some techniques can limit the
overshoot and undershoot at the I/O pins, such as slow slew rate and series
termination, but they are not mandatory. Transmission line effects that cause large
voltage deviation at the receiver are associated with impedance mismatch between
the driver and transmission line. By matching the impedance of the driver to the
characteristic impedance of the transmission line, overshoot voltage can be
significantly reduced. You can use a series termination resistor placed physically close
to the driver to match the total driver impedance to the transmission line impedance.
Stratix III devices support OCT R
banks.
When using a Stratix III device as a receiver, a clamping diode can be used to limit the
overshoot (on-chip or off-chip), but it is not mandatory. Stratix III devices provide an
optional on-chip PCI-clamp diode for column I/O pins. You can use this diode to
protect I/O pins against overshoot voltage.
Another method for limiting overshoot is reducing the bank supply voltage (V
3.0 V. With this method, the clamp diode (on-chip or off-chip), though not mandatory,
can sufficiently clamp overshoot voltage to within the DC and AC input voltage
specification. The clamped voltage can be expressed as the sum of the supply voltage
(V
overshoot and undershoot for all I/O standards, including 3.3-V LVTTL/LVCMOS,
3.0-V LVTTL/LVCMOS, and 3.0-V PCI/PCI-X. Additionally, lowering V
reduces power consumption.
For more information about absolute maximum rating and maximum allowed
overshoot during transitions, refer to the
Devices
In addition to the I/O registers in each IOE, Stratix III devices also have dedicated
registers and phase-shift circuitry on all I/O banks for interfacing with external
memory interfaces.
standards supported by Stratix III devices.
Table 7–4. Memory Interface Standards Supported (Part 1 of 2)
CCIO
) and the diode forward voltage. By lowering V
chapter.
Memory Interface Standard
DDR2 SDRAM
DDR SDRAM
Table 7–4
OL
), input high voltage (V
lists the memory interfaces and the corresponding I/O
S
CCIO
for all LVTTL/LVCMOS I/O standards in all I/O
voltage is powered by 3.3 V or 3.0 V.
DC and Switching Characteristics of Stratix III
IH
), and input low voltage (V
CCIO
Chapter 7: Stratix III Device I/O Features
to 3.0 V you can reduce
I/O Standard
SSTL-18
SSTL-2
© July 2010 Altera Corporation
Stratix III I/O Structure
CCIO
IL
to 3.0 V
OH
) levels
),
CCIO
) to