EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 22

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

xxii
Table 6–17: charge_pump_current Bit Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-48
Table 6–18: loop_filter_r Bit Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-48
Table 6–19: loop_filter_c Bit Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-48
Table 6–20: PLL Counter Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-49
Table 6–21: Dynamic Phase-Shifting Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-49
Table 6–22: Phase Counter Select Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-50
Table 6–23: Chapter Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-53
Table 7–1: I/O Standard Applications for Stratix III Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2
Table 7–2: I/O Standards and Voltage Levels for Stratix III Devices
Table 7–3: Bank Migration Path with Increasing Device Size
Table 7–4: Memory Interface Standards Supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-14
Table 7–5: Programmable Current Strength
Table 7–6: Default Programmable Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-17
Table 7–7: MultiVolt I/O Support for Stratix III Devices
Table 7–8: Selectable I/O Standards with On-Chip Series Termination With or Without Calibration . 7-22
Table 7–9: Selectable I/O Standards with Expanded On-Chip Series Termination with Calibration Range
7-23
Table 7–10: Selectable I/O Standards that Support On-Chip Parallel Termination with Calibration . . 7-24
Table 7–11: On-Chip Differential Termination in Quartus II Software Assignment Editor . . . . . . . . . . . 7-26
Table 7–12: OCT Calibration Block Ports for User Control and Description . . . . . . . . . . . . . . . . . . . . . . . 7-30
Table 7–13: Chapter Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-42
Table 8–1: DQS and DQ Bus Mode Pins for Stratix III Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-5
Table 8–2: Number of DQS/DQ Groups in Stratix III Devices per Side . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-6
Table 8–3: DQ/DQS Group in Stratix III Modular I/O Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-15
Table 8–4: I/O Sub-Bank Combinations for Stratix III Devices that do not have ×36 Groups to form two ×36
Groups. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-16
Table 8–5: DLL Location and Supported I/O Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-23
Table 8–6: DLL Reference Clock Input for EP3SE50, EP3SL50, and EP3SL70 Devices . . . . . . . . . . . . . . . 8-23
Table 8–8: DLL Reference Clock Input for EP3SE80, EP3SE110, EP3SL110, and EP3SL150 Devices in the
1152-pin Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-24
Table 8–7: DLL Reference Clock Input for EP3SE80, EP3SE110, and EP3SL150 Devices in the 780-pin Pack-
age . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-24
Table 8–9: DLL Reference Clock Input for EP3SL200, EP3SE260 and EP3SL340 Devices
Table 8–10: Stratix III DLL Frequency Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-27
Table 8–11: I/O Configuration Block Bit Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-41
Table 8–12: DQS Configuration Block Bit Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-42
Table 8–13: Chapter Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-45
Table 9–1: LVDS Channels Supported in Stratix III Device Side I/O Banks
Table 9–2: LVDS Channels (Emulated) Supported in Stratix III Device Column I/O Banks
9-4
Table 9–3: Differential Bit Naming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-16
Table 9–4: Chapter Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9-27
Table 10–1: Power Supplies Ramp-Up Time (t
Table 10–2: Power Supplies Monitored by the POR Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5
Table 10–3: Power Supplies That Are Not Monitored by the POR Circuitry . . . . . . . . . . . . . . . . . . . . . . . 10-6
Table 10–4: Chapter Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-7
Table 11–1: Stratix III Configuration Schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2
Table 11–2: Stratix III Uncompressed Raw Binary File (.rbf) Sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-2
Table 11–3: Stratix III Configuration Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-3
Table 11–4: Stratix III MSEL Pin Settings for FPP Configuration Schemes . . . . . . . . . . . . . . . . . . . . . . . . . 11-8
Stratix III Device Handbook, Volume 1
(Note 1)
RAMP
) Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10-5
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-16
(Note
(Note 1)
1),
(2)
(Note
. . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-19
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1),
(Note
(3)
© March 2011 Altera Corporation
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1), (2),
(Note
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1),
List of Tables
(2)
1),
. 8-25
(2)
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