EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 423

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

Introduction
Stratix III Security Protection
Security Against Copying
© May 2009 Altera Corporation
SIII51014-1.5
This chapter provides an overview of the design security feature and its
implementation on Stratix
well as security modes available in Stratix III devices.
As Stratix III devices start to play a role in larger and more critical designs in
competitive commercial and military environments, it is increasingly important to
protect the designs from copying, reverse engineering, and tampering. Stratix III
devices address these concerns and are the industry’s only high-density,
high-performance devices with both volatile and non-volatile security feature
support. Stratix III devices have the ability to decrypt configuration bitstreams using
the AES algorithm, an industry standard encryption algorithm that is FIPS-197
certified. They also have a design security feature that utilizes a 256-bit security key.
Altera
(SRAM) configuration cells during device operation. Because SRAM memory is
volatile, SRAM cells must be loaded with configuration data each time the device
powers-up. It is possible to intercept configuration data when it is being transmitted
from the memory source (flash memory or a configuration device) to the device. The
intercepted configuration data could then be used to configure another device.
When using the Stratix III design security feature, the security key is stored in the
Stratix III device. Depending on the security mode, you can configure the Stratix III
device using a configuration file that is encrypted with the same key, or for board
testing, configured with a normal configuration file.
The design security feature is available when configuring Stratix III devices using the
fast passive parallel (FPP) configuration mode with an external host (such as a
MAX
serial (PS) configuration schemes. However, the design security feature is also
available in remote update with fast AS configuration mode. The design security
feature is not available when you are configuring your Stratix III device using Joint
Test Action Group (JTAG)-based configuration. For more information, refer to
“Supported Configuration Schemes” on page
Stratix III device designs are protected from copying, reverse engineering, and
tampering using configuration bitstream encryption.
The security key is securely stored in the Stratix III device and cannot be read out
through any interfaces. In addition, as configuration file read-back is not supported in
Stratix III devices, the design information cannot be copied.
®
®
II device or microprocessor), or when using fast active serial (AS) or passive
Stratix III devices store configuration data in static random access memory
14. Design Security in Stratix III Devices
®
III devices using advanced encryption standard (AES) as
14–5.
Stratix III Device Handbook, Volume 1