EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 184

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

6–36
Figure 6–34. Clock Switchover Using the clkswitch (Manual) Control
Note to
(1) Both inclk0 and inclk1 must be running when the clkswitch signal goes high to initiate a manual clock switchover event.
Stratix III Device Handbook, Volume 1
Figure
6–34:
Manual Override
In the automatic switchover with manual override mode, you can use the clkswitch
input for user- or system-controlled switch conditions. You can use this mode for
same-frequency switchover or to switch between inputs of different frequencies. For
example, if inclk0 is 66 MHz and inclk1 is 200 MHz, you must control the
switchover using clkswitch because the automatic clock-sense circuitry cannot
monitor clock input (inclk0, inclk1) frequencies with a frequency difference of
more than 100% (2×). This feature is useful when the clock sources originate from
multiple cards on the backplane, requiring a system-controlled switchover between
the frequencies of operation. You should choose the backup clock frequency and set
the m, n, c, and k counters accordingly so the VCO operates within the recommended
operating frequency range of 600 to 1,300 MHz. The ALTPLL MegaWizard Plug-in
Manager notifies users if a given combination of inclk0 and inclk1 frequencies
cannot meet this requirement. In the Quartus II software, the VCO value reported is
divided by the post scale counter (K).
Figure 6–34
when controlled by clkswitch. In this case, both clock sources are functional and
inclk0 is selected as the reference clock. clkswitch goes high, which starts the
switchover sequence. On the falling edge of inclk0, the counter's reference clock,
muxout, is gated off to prevent any clock glitching. On the falling edge of inclk1, the
reference clock multiplexer switches from inclk0 to inclk1 as the PLL reference,
and the activeclock signal changes to indicate which clock is currently feeding the
PLL.
In this mode, the activeclock signal mirrors the clkswitch signal. As both clocks
are still functional during the manual switch, neither clkbad signal goes high. Since
the switchover circuit is positive-edge sensitive, the falling edge of the clkswitch
signal does not cause the circuit to switch back from inclk1 to inclk0. When the
clkswitch signal goes high again, the process repeats. clkswitch and automatic
switch only work if the clock being switched to is available. If the clock is not
available, the state machine waits until the clock is available.
activeclock
clkswitch
clkbad0
clkbad1
muxout
inclk0
inclk1
shows an example of a waveform illustrating the switchover feature
(Note 1)
Chapter 6: Clock Networks and PLLs in Stratix III Devices
© July 2010 Altera Corporation
PLLs in Stratix III Devices