EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 138

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

5–32
Stratix III Device Handbook, Volume 1
Table 5–7. Comparison of Round-to-Nearest-Integer and Round-to-Nearest-Even
Two saturation modes are supported in Stratix III:
■
■
You must select one of the two options at compile time.
In 2’s complement format, the maximum negative number that can be represented is
–2
the maximum negative number to –2
■
■
Table 5–8
36-bits.
Table 5–8. Examples of Saturation
(n–1)
Asymmetric saturation mode
Symmetric saturation mode
Asymmetric 32-bit saturation: Max = 0x7FFFFFFF, Min = 0x80000000
Symmetric 32-bit saturation: Max = 0x7FFFFFFF, Min = 0x80000001
44 to 36 Bits Saturation
while the maximum positive number is 2
5926AC01342h
ADA38D2210h
lists how the saturation works. In this example, a 44-bit input is saturated to
Round-To-Nearest-Integer
010111
001101
001010
001110
110111
101101
110110
110010
⇒
⇒
⇒
⇒
⇒
⇒
⇒
⇒
0110
0011
0011
0100
1110
1011
1110
1101
Symmetric SAT Result
(n–1)
800000001h
7FFFFFFFFh
+ 1. For example, for 32 bits:
(n–1)
–1. Symmetrical saturation will limit
Chapter 5: DSP Blocks in Stratix III Devices
Round-To-Nearest-Even
010111
001101
001010
001110
110111
101101
110110
110010
© March 2010 Altera Corporation
Asymmetric SAT Result
Operational Mode Descriptions
⇒
⇒
⇒
⇒
⇒
⇒
⇒
⇒
800000000h
0110
0011
0010
0100
1110
1011
1110
1100
7FFFFFFFFh