EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 276

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

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Stratix III Device Handbook, Volume 1
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1
When using this feature, you must to monitor the DQS delay settings to know how
many offsets you can add and subtract in the system. The DQS delay settings output
by the DLL are also Gray-coded.
For example, if the DLL determines that DQS delay settings of 28 is required to
achieve a 30° phase shift in DLL frequency mode 1, you can subtract up to 28 phase
offset settings and you can add up to 35 phase offset settings to achieve the optimal
delay that you require. However, if the same DQS delay settings of 28 is required to
achieve 30° phase shift in DLL frequency mode 4, you can still subtract up to 28 phase
offset settings, but you can only add up to 3 phase offset settings before the DQS delay
settings reach their maximum settings because DLL frequency mode 4 only uses 5-bit
DLL delay settings.
For more information about the value for each step, refer to the
Characteristics of Stratix III Devices
When using static phase offset, you can specify the phase offset amount in the
ALTMEMPHY megafunction as a positive number for addition or a negative number
for subtraction. You can also have a dynamic phase offset that is always added to,
subtracted from, or both added to and subtracted from the DLL phase shift. When
you always add or subtract, you can dynamically input the phase offset amount into
the dll_offset[5..0] port. When you want to both add and subtract dynamically,
you control the addnsub signal in addition to the dll_offset[5..0] signals.
chapter.
Chapter 8: External Memory Interfaces in Stratix III Devices
Stratix III External Memory Interface Features
© March 2010 Altera Corporation
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