EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 55

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Stratix III Devices
Adaptive Logic Modules
Figure 2–9. Input Function in Normal Mode
Notes to
(1) If datae1 and dataf1 are used as inputs to the six-input function, then datae0 and dataf0 are available for register packing.
(2) The dataf1 input is available for register packing only if the six-input function is un-registered.
Figure 2–10. Template for Supported Seven-Input Functions in Extended LUT Mode
Note to
(1) If the seven-input function is unregistered, the unused eighth input is available for register packing. The second register, reg1, is not available.
© February 2009 Altera Corporation
Figure
Figure
2–10:
2–9:
These inputs are available for register packing.
datae0
datae1
dataf0
dataf1
dataa
datab
datad
datac
(1)
Extended LUT Mode
Use the extended LUT mode to implement a specific set of seven-input functions. The
set must be a 2-to-1 multiplexer fed by two arbitrary five-input functions sharing four
inputs.
extended LUT mode. In this mode, if the seven-input function is unregistered, the
unused eighth input is available for register packing.
Functions that fit into the template shown in
These functions often appear in designs as "if-else" statements in Verilog HDL or
VHDL code.
Arithmetic Mode
The arithmetic mode is ideal for implementing adders, counters, accumulators, wide
parity functions, and comparators. The ALM in arithmetic mode uses two sets of 2
four-input LUTs along with two dedicated full adders. The dedicated adders allow
the LUTs to be available to perform pre-adder logic; therefore, each adder can add the
output of 2 four-input functions.
datae0
datae1
dataf0
dataf1
dataa
datab
datac
datad
(2)
This input is available
for register packing.
Figure 2–10
5-Input
5-Input
LUT
LUT
(Note 1)
shows the template of supported seven-input functions utilizing
6-Input
LUT
labclk
combout0
D
D
D
Figure 2–10
reg0
reg0
reg1
Q
Q
Q
occur naturally in designs.
To general or
To general or
Stratix III Device Handbook, Volume 1
local routing
local routing
To general or
local routing
To general or
local routing
To general or
local routing
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