EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 20

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

xx
List of Figures
sor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12-13
Figure 13–1: IEEE Std. 1149.1 Boundary-Scan Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-1
Figure 13–2: IEEE Std. 1149.1 Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-3
Figure 13–3: Boundary-Scan Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-4
Figure 13–4: Stratix III Device's User I/O BSC with IEEE Std. 1149.1 BST Circuitry . . . . . . . . . . . . . . . . . 13-5
Figure 13–5: IEEE Std. 1149.1 TAP Controller State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-8
Figure 13–6: IEEE Std. 1149.1 Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-9
Figure 13–7: Selecting the Instruction Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-9
Figure 13–8: IEEE Std. 1149.1 BST SAMPLE/PRELOAD Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-11
Figure 13–9: SAMPLE/PRELOAD Shift Data Register Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-12
Figure 13–10: IEEE Std. 1149.1 BST EXTEST Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-13
Figure 13–11: EXTEST Shift Data Register Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-14
Figure 13–12: BYPASS Shift Data Register Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-15
Figure 13–13: JTAG Chain of Mixed Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13-18
Figure 14–1: Design Security
(Note 1)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-4
Figure 14–2: Stratix III Security Modes - Sequence and Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14-6
Figure 15–1: Error Detection Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15-8
Figure 15–2: Enabling the Error Detection CRC Feature in the Quartus II Software . . . . . . . . . . . . . . . . 15-11
Figure 16–1: Stratix III Power Management Example
(Note
1),
(2)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-5
Figure 16–2: TEMPDIODEP and TEMPDIODEN External Pin Connections . . . . . . . . . . . . . . . . . . . . . . . 16-6
Figure 16–3: TSD Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16-6
Stratix III Device Handbook, Volume 1
© March 2011 Altera Corporation