EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 165

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

Chapter 6: Clock Networks and PLLs in Stratix III Devices
Clock Networks in Stratix III Devices
Clock Enable Signals
Figure 6–16. clkena Implementation
Notes to
(1) The R1 and R2 bypass paths are not available for PLL external clock outputs.
(2) The select line is statically controlled by a bit setting in the configuration file (.sof or .pof).
Figure 6–17. clkena Signals
Note to
(1) You can use the clkena signals to enable or disable the global and regional networks or the PLL_<#>_CLKOUT pins.
© July 2010
gate with R2 not bypassed
gate with R2 bypassed
Figure
Figure
output of AND
output of AND
select mux
Altera Corporation
output of
6–17:
6–16:
clkena
clock
output of clock
select mux
Figure 6–16
implemented in Stratix III devices.
In Stratix III devices, the clkena signals are supported at the clock network level
instead of at the PLL output counter level. This allows you to gate off the clock even
when a PLL is not being used. You can also use the clkena signals to control the
dedicated external clocks from the PLLs.
for a clock output enable. clkena is synchronous to the falling edge of the clock
output.
Stratix III devices also have an additional metastability register that aids in
asynchronous enable/disable of the GCLK and RCLK networks. This register can be
optionally bypassed in the Quartus II software.
clkena
shows how the clock enable/disable circuit of the clock control block is
D
(1)
R1
Q
D
R2
(1)
Q
(2)
Figure 6–17
GCLK/
RCLK/
PLL_<#>_CLKOUT (1)
shows the waveform example
Stratix III Device Handbook, Volume 1
6–17