EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 441

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

Chapter 15: SEU Mitigation in Stratix III Devices
Error Detection Timing
Software Support
© March 2010 Altera Corporation
1
The Quartus II software, starting with version 6.1, supports the error detection CRC
feature for Stratix III devices. Enabling this feature generates the CRC_ERROR output
to the optional dual purpose CRC_ERROR pin.
The error detection CRC feature is controlled by the Device and Pin Options dialog
box in the Quartus II software.
Enable the error detection feature using CRC by performing the following steps:
1. Open the Quartus II software and load a project that uses a Stratix III device.
2. On the Assignments menu, click Settings. The Settings dialog box is shown.
3. In the Category list, select Device. The Device page is shown.
4. Click Device and Pin Options. The Device and Pin Options dialog box is shown
5. In the Device and Pin Options dialog box, click the Error Detection CRC tab.
6. Turn on Enable error detection CRC
Figure 15–2. Enabling the Error Detection CRC Feature in the Quartus II Software
7. In the Divide error check frequency by box, enter a valid divisor as documented
The divide value divides the frequency of the configuration oscillator output clock
that clocks the CRC circuitry.
8. Click OK.
(Figure
in
Table 15–5 on page
15–2).
15–9.
(Figure
15–2).
Stratix III Device Handbook, Volume 1
15–11