EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 308

• Manufacturer Part Number: EP3SL150F1152C3N
• Description: IC STRATX III FPGA 150K 1152FBGA
• Manufacturer: Altera
• Series: Stratix® IIIr

Specifications of EP3SL150F1152C3N

• Number Of Logic Elements/cells: 142500
• Number Of Labs/clbs: 5700
• Total Ram Bits: 6390
• Number Of I /o: 744
• Voltage - Supply: 0.86 V ~ 1.15 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-FBGA
• For Use With: 544-2568 - KIT DEVELOPMENT STRATIX III
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Other names: 544-2408; EP3SL150F1152C3NES

9–14
Clocking
Figure 9–13. LVDS/DPA Clocks with Center PLLs for Stratix III Devices
Figure 9–14. LVDS/DPA Clocks with Center and Corner PLLs for Stratix III Devices
Stratix III Device Handbook, Volume 1
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The left/right PLLs feed into the differential transmitter and receive channels through
the LVDS and DPA clock network. The center left/right PLLs can clock the transmitter
and receive channels above and below them. The corner left/right PLLs can drive
I/Os in the banks adjacent to them.
corner PLL clocking in Stratix III devices. You can find more information about PLL
clocking restrictions in
LVDS
Clock
LVDS
Clock
LVDS
LVDS
Clock
Clock
PLL_L2
PLL_L3
Center
Center
PLL_L2
PLL_L3
PLL_L4
Center
Center
Corner
Corner
PLL_L1
Clock
Clock
Clock
Clock
DPA
DPA
DPA
DPA
“Differential Pin Placement Guidelines” on page
Quadrant
Quadrant
Quadrant
Quadrant
Chapter 9: High-Speed Differential I/O Interfaces and DPA in Stratix III Devices
Quadrant
Quadrant
Figure 9–13
Quadrant
Quadrant
and
Figure 9–14
Clock
Clock
Clock
Clock
DPA
DPA
DPA
DPA
PLL_R1
PLL_R2
PLL_R3
PLL_R2
PLL_R3
PLL_R4
Corner
Center
Center
Corner
Center
Center
LVDS
Clock
LVDS
Clock
LVDS
Clock
LVDS
Clock
© July 2010 Altera Corporation
show center and
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9–19.
Clocking