EP3SL150F1152C3N Altera, EP3SL150F1152C3N Datasheet - Page 61
![IC STRATX III FPGA 150K 1152FBGA](/photos/6/72/67293/544-1152-fbga_sml.jpg)
EP3SL150F1152C3N
Manufacturer Part Number
EP3SL150F1152C3N
Description
IC STRATX III FPGA 150K 1152FBGA
Manufacturer
Altera
Series
Stratix® IIIr
Datasheets
1.EP3SL150F780C4N.pdf
(16 pages)
2.EP3SL150F780C4N.pdf
(332 pages)
3.EP3SL150F780C4N.pdf
(456 pages)
Specifications of EP3SL150F1152C3N
Number Of Logic Elements/cells
142500
Number Of Labs/clbs
5700
Total Ram Bits
6390
Number Of I /o
744
Voltage - Supply
0.86 V ~ 1.15 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-FBGA
For Use With
544-2568 - KIT DEVELOPMENT STRATIX III
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Other names
544-2408
EP3SL150F1152C3NES
EP3SL150F1152C3NES
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP3SL150F1152C3N
Manufacturer:
ALTERA
Quantity:
490
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Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Stratix III Devices
Adaptive Logic Modules
Figure 2–15. LUT Register from Two Combinational Blocks
© February 2009 Altera Corporation
datain(datac)
1
aclr
sclr
clk
Refer to
arithmetic chain interconnect.
LUT-Register Mode
LUT-Register mode allows third register capability within an ALM. Two internal
feedback loops allow combinational ALUT1 to implement the master latch and
combinational ALUT0 to implement the slave latch needed for the third register. The
LUT register shares its clock, clock enable, and asynchronous clear sources with the
top dedicated register.
combinational blocks within the ALM.
mode.
“ALM Interconnects” on page 2–20
Figure 2–15
shows the register constructed using two
Figure 2–16
for more information on shared
4-input
5-input
LUT
LUT
shows the ALM in LUT-Register
combout
combout
sumout
sumout
Stratix III Device Handbook, Volume 1
LUT regout
2–17
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